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https://github.com/espressif/binutils-gdb.git
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* config/tc-m68k.c (m68k_ip): If instruction is invalid for the
selected architecture, print a message saying so and listing what processors support it, rather than saying "operands mismatch".
This commit is contained in:
Ken Raeburn
@ -992,6 +992,7 @@ void m68k_ip (instring)
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char *crack_operand();
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char *crack_operand();
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LITTLENUM_TYPE words[6];
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LITTLENUM_TYPE words[6];
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LITTLENUM_TYPE *wordp;
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LITTLENUM_TYPE *wordp;
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unsigned long ok_arch = 0;
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if (*instring == ' ')
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if (*instring == ' ')
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instring++; /* skip leading whitespace */
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instring++; /* skip leading whitespace */
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@ -1048,7 +1049,6 @@ void m68k_ip (instring)
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for(n=opsfound;n>0;--n)
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for(n=opsfound;n>0;--n)
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the_ins.operands[n]=the_ins.operands[n-1];
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the_ins.operands[n]=the_ins.operands[n-1];
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/* memcpy((char *)(&the_ins.operands[1]), (char *)(&the_ins.operands[0]), opsfound*sizeof(the_ins.operands[0])); */
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memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
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memset((char *)(&the_ins.operands[0]), '\0', sizeof(the_ins.operands[0]));
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the_ins.operands[0].mode=MSCR;
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the_ins.operands[0].mode=MSCR;
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the_ins.operands[0].reg=COPNUM; /* COP #1 */
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the_ins.operands[0].reg=COPNUM; /* COP #1 */
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@ -1062,325 +1062,327 @@ void m68k_ip (instring)
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then reject this pattern. */
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then reject this pattern. */
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if (opsfound != opcode->m_opnum
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if (opsfound != opcode->m_opnum
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|| ((opcode->m_arch & current_architecture) == 0)) {
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|| ((opcode->m_arch & current_architecture) == 0))
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{
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++losing;
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ok_arch |= opcode->m_arch;
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}
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else {
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for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
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/* Warning: this switch is huge! */
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/* I've tried to organize the cases into this order:
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non-alpha first, then alpha by letter. lower-case goes directly
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before uppercase counterpart. */
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/* Code with multiple case ...: gets sorted by the lowest case ...
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it belongs to. I hope this makes sense. */
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switch(*s) {
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case '!':
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if (opP->mode == MSCR || opP->mode == IMMED
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|| opP->mode == DREG || opP->mode == AREG
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|| opP->mode == AINC || opP->mode == ADEC
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|| opP->mode == REGLST)
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losing++;
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break;
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++losing;
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case '#':
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if(opP->mode!=IMMED)
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losing++;
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else {
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long t;
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} else {
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t=get_num(opP->con1,80);
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for (s=opcode->m_operands, opP = &the_ins.operands[0]; *s && !losing; s += 2, opP++) {
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if(s[1]=='b' && !isbyte(t))
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/* Warning: this switch is huge! */
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losing++;
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/* I've tried to organize the cases into this order:
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else if(s[1]=='w' && !isword(t))
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non-alpha first, then alpha by letter. lower-case goes directly
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losing++;
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before uppercase counterpart. */
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}
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/* Code with multiple case ...: gets sorted by the lowest case ...
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break;
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it belongs to. I hope this makes sense. */
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switch(*s) {
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case '!':
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if (opP->mode == MSCR || opP->mode == IMMED
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|| opP->mode == DREG || opP->mode == AREG
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|| opP->mode == AINC || opP->mode == ADEC
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|| opP->mode == REGLST)
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losing++;
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break;
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case '#':
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case '^':
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if(opP->mode!=IMMED)
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case 'T':
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losing++;
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if(opP->mode!=IMMED)
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else {
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losing++;
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long t;
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break;
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t=get_num(opP->con1,80);
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case '$':
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if(s[1]=='b' && !isbyte(t))
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if(opP->mode==MSCR || opP->mode==AREG ||
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losing++;
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opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
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else if(s[1]=='w' && !isword(t))
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losing++;
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losing++;
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break;
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}
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break;
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case '^':
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case '%':
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case 'T':
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if(opP->mode==MSCR || opP->reg==PC ||
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if(opP->mode!=IMMED)
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opP->reg==ZPC || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '$':
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if(opP->mode==MSCR || opP->mode==AREG ||
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opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
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losing++;
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break;
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case '%':
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if(opP->mode==MSCR || opP->reg==PC ||
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opP->reg==ZPC || opP->mode==REGLST)
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losing++;
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break;
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case '&':
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case '&':
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if(opP->mode==MSCR || opP->mode==DREG ||
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if(opP->mode==MSCR || opP->mode==DREG ||
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opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
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opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC ||
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opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
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opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '*':
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case '*':
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if(opP->mode==MSCR || opP->mode==REGLST)
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if(opP->mode==MSCR || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '+':
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case '+':
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if(opP->mode!=AINC)
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if(opP->mode!=AINC)
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losing++;
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losing++;
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break;
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break;
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case '-':
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case '-':
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if(opP->mode!=ADEC)
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if(opP->mode!=ADEC)
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losing++;
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losing++;
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break;
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break;
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case '/':
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case '/':
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if(opP->mode==MSCR || opP->mode==AREG ||
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if(opP->mode==MSCR || opP->mode==AREG ||
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opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
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opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case ';':
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case ';':
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if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
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if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '?':
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case '?':
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if(opP->mode==MSCR || opP->mode==AREG ||
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if(opP->mode==MSCR || opP->mode==AREG ||
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opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
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opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC ||
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opP->reg==ZPC || opP->mode==REGLST)
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opP->reg==ZPC || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '@':
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case '@':
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if(opP->mode==MSCR || opP->mode==AREG ||
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if(opP->mode==MSCR || opP->mode==AREG ||
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opP->mode==IMMED || opP->mode==REGLST)
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opP->mode==IMMED || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case '~': /* For now! (JF FOO is this right?) */
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case '~': /* For now! (JF FOO is this right?) */
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if(opP->mode==MSCR || opP->mode==DREG ||
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if(opP->mode==MSCR || opP->mode==DREG ||
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opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
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opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST)
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losing++;
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losing++;
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break;
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break;
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case 'A':
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case 'A':
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if(opP->mode!=AREG)
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if(opP->mode!=AREG)
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losing++;
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losing++;
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break;
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break;
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case 'a':
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case 'a':
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if (opP->mode != AINDR) {
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if (opP->mode != AINDR) {
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++losing;
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++losing;
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} /* if not address register indirect */
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} /* if not address register indirect */
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break;
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break;
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case 'B': /* FOO */
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case 'B': /* FOO */
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if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
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if(opP->mode!=ABSL || (flagseen['S'] && instring[0] == 'j'
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&& instring[1] == 'b'
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&& instring[1] == 'b'
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&& instring[2] == 's'
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&& instring[2] == 's'
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&& instring[3] == 'r'))
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&& instring[3] == 'r'))
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losing++;
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losing++;
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break;
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break;
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case 'C':
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case 'C':
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if(opP->mode!=MSCR || opP->reg!=CCR)
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if(opP->mode!=MSCR || opP->reg!=CCR)
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losing++;
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losing++;
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break;
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break;
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case 'd': /* FOO This mode is a KLUDGE!! */
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case 'd': /* FOO This mode is a KLUDGE!! */
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if(opP->mode!=AOFF && (opP->mode!=ABSL ||
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if(opP->mode!=AOFF && (opP->mode!=ABSL ||
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opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
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opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')'))
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losing++;
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losing++;
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break;
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break;
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case 'D':
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case 'D':
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if(opP->mode!=DREG)
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if(opP->mode!=DREG)
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losing++;
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losing++;
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break;
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break;
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case 'F':
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case 'F':
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if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
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if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7))
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losing++;
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losing++;
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break;
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break;
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case 'I':
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case 'I':
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if(opP->mode!=MSCR || opP->reg<COPNUM ||
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if(opP->mode!=MSCR || opP->reg<COPNUM ||
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opP->reg>=COPNUM+7)
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opP->reg>=COPNUM+7)
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losing++;
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losing++;
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break;
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break;
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case 'J':
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case 'J':
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if (opP->mode != MSCR
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if (opP->mode != MSCR
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|| opP->reg < USP
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|| opP->reg < USP
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|| opP->reg > URP
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|| opP->reg > URP
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|| cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
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|| cpu_of_arch(current_architecture) < m68010 /* before 68010 had none */
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|| (cpu_of_arch(current_architecture) < m68020
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|| (cpu_of_arch(current_architecture) < m68020
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&& opP->reg != SFC
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&& opP->reg != SFC
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&& opP->reg != DFC
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&& opP->reg != DFC
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&& opP->reg != USP
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&& opP->reg != USP
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&& opP->reg != VBR) /* 68010's had only these */
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&& opP->reg != VBR) /* 68010's had only these */
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|| (cpu_of_arch(current_architecture) < m68040
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|| (cpu_of_arch(current_architecture) < m68040
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&& opP->reg != SFC
|
&& opP->reg != SFC
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&& opP->reg != DFC
|
&& opP->reg != DFC
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&& opP->reg != USP
|
&& opP->reg != USP
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&& opP->reg != VBR
|
&& opP->reg != VBR
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&& opP->reg != CACR
|
&& opP->reg != CACR
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&& opP->reg != CAAR
|
&& opP->reg != CAAR
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&& opP->reg != MSP
|
&& opP->reg != MSP
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&& opP->reg != ISP) /* 680[23]0's have only these */
|
&& opP->reg != ISP) /* 680[23]0's have only these */
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|| (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
|
|| (cpu_of_arch(current_architecture) == m68040 /* 68040 has all but this */
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&& opP->reg == CAAR)) {
|
&& opP->reg == CAAR)) {
|
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losing++;
|
losing++;
|
||||||
} /* doesn't cut it */
|
} /* doesn't cut it */
|
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break;
|
break;
|
||||||
|
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case 'k':
|
case 'k':
|
||||||
if(opP->mode!=IMMED)
|
if(opP->mode!=IMMED)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'l':
|
case 'l':
|
||||||
case 'L':
|
case 'L':
|
||||||
if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
|
if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) {
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if(s[1]=='8')
|
if(s[1]=='8')
|
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losing++;
|
losing++;
|
||||||
else {
|
else {
|
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opP->mode=REGLST;
|
opP->mode=REGLST;
|
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opP->reg=1<<(opP->reg-DATA);
|
opP->reg=1<<(opP->reg-DATA);
|
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}
|
}
|
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} else if(opP->mode!=REGLST) {
|
} else if(opP->mode!=REGLST) {
|
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losing++;
|
losing++;
|
||||||
} else if(s[1]=='8' && opP->reg&0x0FFffFF)
|
} else if(s[1]=='8' && opP->reg&0x0FFffFF)
|
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losing++;
|
losing++;
|
||||||
else if(s[1]=='3' && opP->reg&0x7000000)
|
else if(s[1]=='3' && opP->reg&0x7000000)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'M':
|
case 'M':
|
||||||
if(opP->mode!=IMMED)
|
if(opP->mode!=IMMED)
|
||||||
losing++;
|
losing++;
|
||||||
else {
|
else {
|
||||||
long t;
|
long t;
|
||||||
|
|
||||||
t=get_num(opP->con1,80);
|
t=get_num(opP->con1,80);
|
||||||
if(!issbyte(t) || isvar(opP->con1))
|
if(!issbyte(t) || isvar(opP->con1))
|
||||||
losing++;
|
losing++;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'O':
|
case 'O':
|
||||||
if(opP->mode!=DREG && opP->mode!=IMMED)
|
if(opP->mode!=DREG && opP->mode!=IMMED)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'Q':
|
case 'Q':
|
||||||
if(opP->mode!=IMMED)
|
if(opP->mode!=IMMED)
|
||||||
losing++;
|
losing++;
|
||||||
else {
|
else {
|
||||||
long t;
|
long t;
|
||||||
|
|
||||||
t=get_num(opP->con1,80);
|
t=get_num(opP->con1,80);
|
||||||
if(t<1 || t>8 || isvar(opP->con1))
|
if(t<1 || t>8 || isvar(opP->con1))
|
||||||
losing++;
|
losing++;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'R':
|
case 'R':
|
||||||
if(opP->mode!=DREG && opP->mode!=AREG)
|
if(opP->mode!=DREG && opP->mode!=AREG)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 's':
|
case 's':
|
||||||
if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
|
if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC))
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'S':
|
case 'S':
|
||||||
if(opP->mode!=MSCR || opP->reg!=SR)
|
if(opP->mode!=MSCR || opP->reg!=SR)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'U':
|
case 'U':
|
||||||
if(opP->mode!=MSCR || opP->reg!=USP)
|
if(opP->mode!=MSCR || opP->reg!=USP)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
/* JF these are out of order. We could put them
|
/* JF these are out of order. We could put them
|
||||||
in order if we were willing to put up with
|
in order if we were willing to put up with
|
||||||
bunches of #ifdef m68851s in the code */
|
bunches of #ifdef m68851s in the code */
|
||||||
#ifndef NO_68851
|
#ifndef NO_68851
|
||||||
/* Memory addressing mode used by pflushr */
|
/* Memory addressing mode used by pflushr */
|
||||||
case '|':
|
case '|':
|
||||||
if(opP->mode==MSCR || opP->mode==DREG ||
|
if(opP->mode==MSCR || opP->mode==DREG ||
|
||||||
opP->mode==AREG || opP->mode==REGLST)
|
opP->mode==AREG || opP->mode==REGLST)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'f':
|
case 'f':
|
||||||
if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
|
if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC))
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'P':
|
case 'P':
|
||||||
if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
|
if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL &&
|
||||||
opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
|
opP->reg != VAL && opP->reg != SCC && opP->reg != AC))
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'V':
|
case 'V':
|
||||||
if (opP->reg != VAL)
|
if (opP->reg != VAL)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'W':
|
case 'W':
|
||||||
if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
|
if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP &&
|
||||||
opP->reg != CRP))
|
opP->reg != CRP))
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'X':
|
case 'X':
|
||||||
if (opP->mode != MSCR ||
|
if (opP->mode != MSCR ||
|
||||||
(!(opP->reg >= BAD && opP->reg <= BAD+7) &&
|
(!(opP->reg >= BAD && opP->reg <= BAD+7) &&
|
||||||
!(opP->reg >= BAC && opP->reg <= BAC+7)))
|
!(opP->reg >= BAC && opP->reg <= BAC+7)))
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'Y':
|
case 'Y':
|
||||||
if (opP->reg != PSR)
|
if (opP->reg != PSR)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 'Z':
|
case 'Z':
|
||||||
if (opP->reg != PCSR)
|
if (opP->reg != PCSR)
|
||||||
losing++;
|
losing++;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
case 'c':
|
case 'c':
|
||||||
if (opP->reg != NC
|
if (opP->reg != NC
|
||||||
&& opP->reg != IC
|
&& opP->reg != IC
|
||||||
&& opP->reg != DC
|
&& opP->reg != DC
|
||||||
&& opP->reg != BC) {
|
&& opP->reg != BC) {
|
||||||
losing++;
|
losing++;
|
||||||
} /* not a cache specifier. */
|
} /* not a cache specifier. */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case '_':
|
case '_':
|
||||||
if (opP->mode != ABSL) {
|
if (opP->mode != ABSL) {
|
||||||
++losing;
|
++losing;
|
||||||
} /* not absolute */
|
} /* not absolute */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
|
as_fatal("Internal error: Operand mode %c unknown in line %s of file \"%s\"",
|
||||||
*s, __LINE__, __FILE__);
|
*s, __LINE__, __FILE__);
|
||||||
} /* switch on type of operand */
|
} /* switch on type of operand */
|
||||||
|
|
||||||
if (losing) break;
|
if (losing)
|
||||||
} /* for each operand */
|
break;
|
||||||
} /* if immediately wrong */
|
} /* for each operand */
|
||||||
|
} /* if immediately wrong */
|
||||||
|
|
||||||
if (!losing) {
|
if (!losing) {
|
||||||
break;
|
break;
|
||||||
@ -1389,7 +1391,67 @@ void m68k_ip (instring)
|
|||||||
opcode = opcode->m_next;
|
opcode = opcode->m_next;
|
||||||
|
|
||||||
if (!opcode) {
|
if (!opcode) {
|
||||||
the_ins.error = "instruction/operands mismatch or invalid\n instruction for this architecture";
|
if (ok_arch)
|
||||||
|
{
|
||||||
|
char buf[200], *cp;
|
||||||
|
int len;
|
||||||
|
strcpy (buf, "invalid instruction for this architecture; needs ");
|
||||||
|
cp = buf + strlen (buf);
|
||||||
|
switch (ok_arch)
|
||||||
|
{
|
||||||
|
case mfloat:
|
||||||
|
strcpy (cp, "fpu");
|
||||||
|
break;
|
||||||
|
case mmmu:
|
||||||
|
strcpy (cp, "mmu");
|
||||||
|
break;
|
||||||
|
case m68020up:
|
||||||
|
strcpy (cp, "68020 or higher");
|
||||||
|
break;
|
||||||
|
case m68000up:
|
||||||
|
strcpy (cp, "68000 or higher");
|
||||||
|
break;
|
||||||
|
case m68010up:
|
||||||
|
strcpy (cp, "68010 or higher");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
{
|
||||||
|
int got_one = 0, idx;
|
||||||
|
const static struct {
|
||||||
|
enum m68k_architecture arch;
|
||||||
|
const char *name;
|
||||||
|
} archs[] = {
|
||||||
|
m68000, "68000",
|
||||||
|
m68010, "68010",
|
||||||
|
m68020, "68020",
|
||||||
|
m68030, "68030",
|
||||||
|
m68040, "68040",
|
||||||
|
m68881, "68881",
|
||||||
|
m68851, "68851",
|
||||||
|
};
|
||||||
|
for (idx = 0; idx < sizeof (archs)/sizeof (archs[0]); idx++)
|
||||||
|
{
|
||||||
|
if (archs[idx].arch & ok_arch)
|
||||||
|
{
|
||||||
|
if (got_one)
|
||||||
|
{
|
||||||
|
strcpy (cp, " or ");
|
||||||
|
cp += strlen (cp);
|
||||||
|
}
|
||||||
|
got_one = 1;
|
||||||
|
strcpy (cp, archs[idx].name);
|
||||||
|
cp += strlen (cp);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
len = cp - buf + 1;
|
||||||
|
cp = malloc (len);
|
||||||
|
strcpy (cp, buf);
|
||||||
|
the_ins.error = cp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
the_ins.error = "operands mismatch";
|
||||||
return;
|
return;
|
||||||
} /* Fell off the end */
|
} /* Fell off the end */
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user