X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode

Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80
in 32-bit mode.

gas/

	PR binutils/20754
	* testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
	* testsuite/gas/i386/opcode-intel.d: Updated.
	* testsuite/gas/i386/opcode.d: Likewise.

opcodes/

	PR binutils/20754
	* i386-dis.c (REG_82): New.
	(X86_64_82_REG_0): Likewise.
	(X86_64_82_REG_1): Likewise.
	(X86_64_82_REG_2): Likewise.
	(X86_64_82_REG_3): Likewise.
	(X86_64_82_REG_4): Likewise.
	(X86_64_82_REG_5): Likewise.
	(X86_64_82_REG_6): Likewise.
	(X86_64_82_REG_7): Likewise.
	(dis386): Use REG_82.
	(reg_table): Add REG_82.
	(x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
	X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
	X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
This commit is contained in:
H.J. Lu
2016-11-03 09:13:01 -07:00
parent 722bcb33bf
commit 8b89fe14b5
6 changed files with 111 additions and 1 deletions

@ -1,3 +1,10 @@
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20754
* testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode.d: Likewise.
2016-11-02 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (SBIT_SHIFT): New.

@ -592,4 +592,12 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp dx,WORD PTR \[eax-0x6f6f6f70\]
+[a-f0-9]+: 82 c3 01 add bl,0x1
+[a-f0-9]+: 82 f3 01 xor bl,0x1
+[a-f0-9]+: 82 d3 01 adc bl,0x1
+[a-f0-9]+: 82 db 01 sbb bl,0x1
+[a-f0-9]+: 82 e3 01 and bl,0x1
+[a-f0-9]+: 82 eb 01 sub bl,0x1
+[a-f0-9]+: 82 f3 01 xor bl,0x1
+[a-f0-9]+: 82 fb 01 cmp bl,0x1
#pass

@ -591,4 +591,12 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%dx
+[a-f0-9]+: 82 c3 01 add \$0x1,%bl
+[a-f0-9]+: 82 f3 01 xor \$0x1,%bl
+[a-f0-9]+: 82 d3 01 adc \$0x1,%bl
+[a-f0-9]+: 82 db 01 sbb \$0x1,%bl
+[a-f0-9]+: 82 e3 01 and \$0x1,%bl
+[a-f0-9]+: 82 eb 01 sub \$0x1,%bl
+[a-f0-9]+: 82 f3 01 xor \$0x1,%bl
+[a-f0-9]+: 82 fb 01 cmp \$0x1,%bl
#pass

@ -589,3 +589,12 @@ foo:
cmovpo 0x90909090(%eax),%edx
cmovpe 0x90909090(%eax),%dx
cmovpo 0x90909090(%eax),%dx
.byte 0x82, 0xc3, 0x01
.byte 0x82, 0xf3, 0x01
.byte 0x82, 0xd3, 0x01
.byte 0x82, 0xdb, 0x01
.byte 0x82, 0xe3, 0x01
.byte 0x82, 0xeb, 0x01
.byte 0x82, 0xf3, 0x01
.byte 0x82, 0xfb, 0x01

@ -1,3 +1,21 @@
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20754
* i386-dis.c (REG_82): New.
(X86_64_82_REG_0): Likewise.
(X86_64_82_REG_1): Likewise.
(X86_64_82_REG_2): Likewise.
(X86_64_82_REG_3): Likewise.
(X86_64_82_REG_4): Likewise.
(X86_64_82_REG_5): Likewise.
(X86_64_82_REG_6): Likewise.
(X86_64_82_REG_7): Likewise.
(dis386): Use REG_82.
(reg_table): Add REG_82.
(x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (REG_82): Renamed to ...

@ -706,6 +706,7 @@ enum
{
REG_80 = 0,
REG_81,
REG_82,
REG_83,
REG_8F,
REG_C0,
@ -1694,6 +1695,14 @@ enum
X86_64_63,
X86_64_6D,
X86_64_6F,
X86_64_82_REG_0,
X86_64_82_REG_1,
X86_64_82_REG_2,
X86_64_82_REG_3,
X86_64_82_REG_4,
X86_64_82_REG_5,
X86_64_82_REG_6,
X86_64_82_REG_7,
X86_64_9A,
X86_64_C4,
X86_64_C5,
@ -2662,7 +2671,7 @@ static const struct dis386 dis386[] = {
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
{ Bad_Opcode },
{ REG_TABLE (REG_82) },
{ REG_TABLE (REG_83) },
{ "testB", { Eb, Gb }, 0 },
{ "testS", { Ev, Gv }, 0 },
@ -3400,6 +3409,17 @@ static const struct dis386 reg_table[][8] = {
{ "xorQ", { Evh1, Iv }, 0 },
{ "cmpQ", { Ev, Iv }, 0 },
},
/* REG_82 */
{
{ X86_64_TABLE (X86_64_82_REG_0) },
{ X86_64_TABLE (X86_64_82_REG_1) },
{ X86_64_TABLE (X86_64_82_REG_2) },
{ X86_64_TABLE (X86_64_82_REG_3) },
{ X86_64_TABLE (X86_64_82_REG_4) },
{ X86_64_TABLE (X86_64_82_REG_5) },
{ X86_64_TABLE (X86_64_82_REG_6) },
{ X86_64_TABLE (X86_64_82_REG_7) },
},
/* REG_83 */
{
{ "addQ", { Evh1, sIb }, 0 },
@ -6887,6 +6907,46 @@ static const struct dis386 x86_64_table[][2] = {
{ "outs{G|}", { indirDXr, Xz }, 0 },
},
/* X86_64_82_REG_0 */
{
{ "addA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_1 */
{
{ "orA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_2 */
{
{ "adcA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_3 */
{
{ "sbbA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_4 */
{
{ "andA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_5 */
{
{ "subA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_6 */
{
{ "xorA", { Ebh1, Ib }, 0 },
},
/* X86_64_82_REG_7 */
{
{ "cmpA", { Eb, Ib }, 0 },
},
/* X86_64_9A */
{
{ "Jcall{T|}", { Ap }, 0 },