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* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for

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the two drem and the two dremu macros.
This commit is contained in:
Adam Nemet
2008-04-29 23:27:01 +00:00
parent 1de34ab72d
commit 89aa3097c2
2 changed files with 9 additions and 4 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
the two drem and the two dremu macros.
2008-04-28 Adam Nemet <anemet@caviumnetworks.com> 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
* mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1

8
opcodes/mips-opc.c
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@ -630,11 +630,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, {"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3 },
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, {"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, {"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, {"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },