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https://github.com/espressif/binutils-gdb.git
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sim: v850: rename v850.dc to align with other ports
Other arches use the .dc extension for the instruction decode table.
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@ -1628,7 +1628,7 @@ testsuite_common_CPPFLAGS = \
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850-dc
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@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc
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all: config.h
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all: config.h
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$(MAKE) $(AM_MAKEFLAGS) all-recursive
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$(MAKE) $(AM_MAKEFLAGS) all-recursive
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@ -51,7 +51,7 @@ $(%C%_BUILT_SRC_FROM_IGEN): %D%/stamp-igen
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%C%_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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%C%_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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%C%_IGEN_INSN = $(srcdir)/%D%/v850.igen
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%C%_IGEN_INSN = $(srcdir)/%D%/v850.igen
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%C%_IGEN_DC = $(srcdir)/%D%/v850-dc
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%C%_IGEN_DC = $(srcdir)/%D%/v850.dc
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%D%/stamp-igen: $(%C%_IGEN_INSN) $(%C%_IGEN_DC) $(IGEN)
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%D%/stamp-igen: $(%C%_IGEN_INSN) $(%C%_IGEN_DC) $(IGEN)
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$(AM_V_GEN)$(IGEN_RUN) \
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$(AM_V_GEN)$(IGEN_RUN) \
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$(%C%_IGEN_TRACE) \
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$(%C%_IGEN_TRACE) \
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