From 86dc452e25064ad7c855adb19b074f498d581bda Mon Sep 17 00:00:00 2001
From: Doug Evans <dje@google.com>
Date: Mon, 30 Nov 1998 23:41:55 +0000
Subject: [PATCH] * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE ->
CGEN_INSN_BASE_VALUE. * cgen-asm.in (insert_normal): Change start,length to
unsigned int. New args word_offset, word_length. Rewrite. (FLD): Define.
(insert_1): Fix lsb0 case. * cgen-dis.in (extract_normal): Change
start,length to unsigned int. New args word_offset, word_length. Rewrite.
(FLD): Define. (extract_1): Fix lsb0 case. * cgen-opc.in (FLD):
Define. * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
* fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate.
---
opcodes/cgen-opc.in | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/opcodes/cgen-opc.in b/opcodes/cgen-opc.in
index 2bb47a1d508..44a187dd80f 100644
--- a/opcodes/cgen-opc.in
+++ b/opcodes/cgen-opc.in
@@ -30,6 +30,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "@prefix@-opc.h"
#include "opintl.h"
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
@@ -98,7 +101,8 @@ const CGEN_INSN *
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
- if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((base_insn & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,