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Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.

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PR target/19721
opcodes	* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
	of MOV insn that aliases an ORR insn.

gas	* testsuite/gas/aarch64/pr19721.s: New test source file.
	* testsuite/gas/aarch64/pr19721.d: New test driver file.
This commit is contained in:
Nick Clifton
2016-03-18 17:02:20 +00:00
parent 9c3f22346d
commit 8678914fcb
5 changed files with 26 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gas/ChangeLog
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@ -1,5 +1,9 @@
2016-03-18 Nick Clifton <nickc@redhat.com> 2016-03-18 Nick Clifton <nickc@redhat.com>
PR target/19721
* testsuite/gas/aarch64/pr19721.s: New test source file.
* testsuite/gas/aarch64/pr19721.d: New test driver file.
* doc/as.texinfo: Place the target specific command line options * doc/as.texinfo: Place the target specific command line options
into their own man page section. into their own man page section.

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gas/testsuite/gas/aarch64/pr19721.d Normal file
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@ -0,0 +1,10 @@
#objdump: -d
.*: file format .*
Disassembly of section \.text:
0+000 <.*>:
0: aa1103e7 mov x7, x17
4: aa1167e7 mov x7, x17, lsl #25
8: aa1167e7 mov x7, x17, lsl #25

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gas/testsuite/gas/aarch64/pr19721.s Normal file
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@ -0,0 +1,5 @@
.text
mov x7, x17
mov x7, x17, lsl 25
orr x7, xzr, x17, lsl 25

6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2016-03-18 Nick Clifton <nickc@redhat.com>
PR target/19721
* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
of MOV insn that aliases an ORR insn.
2016-03-16 Jiong Wang <jiong.wang@arm.com> 2016-03-16 Jiong Wang <jiong.wang@arm.com>
* arm-dis.c (neon_opcodes): Support new FP16 instructions. * arm-dis.c (neon_opcodes): Support new FP16 instructions.

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opcodes/aarch64-tbl.h
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@ -2547,7 +2547,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
{"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
{"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
{"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF}, {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
{"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO}, {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO},
{"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF}, {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
{"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF}, {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},