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[gdb] Fix more typos in comments

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Fix typos in comments.  NFC.

Tested on x86_64-linux.

gdb/ChangeLog:

2019-10-18  Tom de Vries  <tdevries@suse.de>

	* aarch64-tdep.c: Fix typos in comments.
	* ada-lang.c: Same.
	* ada-tasks.c: Same.
	* alpha-tdep.c: Same.
	* alpha-tdep.h: Same.
	* amd64-nat.c: Same.
	* amd64-windows-tdep.c: Same.
	* arc-tdep.c: Same.
	* arc-tdep.h: Same.
	* arch-utils.c: Same.
	* arm-nbsd-tdep.c: Same.
	* arm-tdep.c: Same.
	* ax-gdb.c: Same.
	* blockframe.c: Same.
	* btrace.c: Same.
	* c-varobj.c: Same.
	* coff-pe-read.c: Same.
	* coffread.c: Same.
	* cris-tdep.c: Same.
	* darwin-nat.c: Same.
	* dbxread.c: Same.
	* dcache.c: Same.
	* disasm.c: Same.
	* dtrace-probe.c: Same.
	* dwarf-index-write.c: Same.
	* dwarf2-frame-tailcall.c: Same.
	* dwarf2-frame.c: Same.
	* dwarf2read.c: Same.
	* eval.c: Same.
	* exceptions.c: Same.
	* fbsd-tdep.c: Same.
	* findvar.c: Same.
	* frame.c: Same.
	* frv-tdep.c: Same.
	* gnu-v3-abi.c: Same.
	* go32-nat.c: Same.
	* h8300-tdep.c: Same.
	* hppa-tdep.c: Same.
	* i386-linux-tdep.c: Same.
	* i386-tdep.c: Same.
	* ia64-libunwind-tdep.c: Same.
	* ia64-tdep.c: Same.
	* infcmd.c: Same.
	* infrun.c: Same.
	* linespec.c: Same.
	* linux-nat.c: Same.
	* linux-thread-db.c: Same.
	* machoread.c: Same.
	* mdebugread.c: Same.
	* mep-tdep.c: Same.
	* mn10300-tdep.c: Same.
	* namespace.c: Same.
	* objfiles.c: Same.
	* opencl-lang.c: Same.
	* or1k-tdep.c: Same.
	* osabi.c: Same.
	* ppc-linux-nat.c: Same.
	* ppc-linux-tdep.c: Same.
	* ppc-sysv-tdep.c: Same.
	* printcmd.c: Same.
	* procfs.c: Same.
	* record-btrace.c: Same.
	* record-full.c: Same.
	* remote-fileio.c: Same.
	* remote.c: Same.
	* rs6000-tdep.c: Same.
	* s12z-tdep.c: Same.
	* score-tdep.c: Same.
	* ser-base.c: Same.
	* ser-go32.c: Same.
	* skip.c: Same.
	* sol-thread.c: Same.
	* solib-svr4.c: Same.
	* solib.c: Same.
	* source.c: Same.
	* sparc-nat.c: Same.
	* sparc-sol2-tdep.c: Same.
	* sparc-tdep.c: Same.
	* sparc64-tdep.c: Same.
	* stabsread.c: Same.
	* stack.c: Same.
	* symfile.c: Same.
	* symtab.c: Same.
	* target-descriptions.c: Same.
	* target-float.c: Same.
	* thread.c: Same.
	* utils.c: Same.
	* valops.c: Same.
	* valprint.c: Same.
	* value.c: Same.
	* varobj.c: Same.
	* windows-nat.c: Same.
	* xcoffread.c: Same.
	* xstormy16-tdep.c: Same.
	* xtensa-tdep.c: Same.

Change-Id: I5175f1b107bfa4e1cdd4a3361ccb4739e53c75c4
This commit is contained in:
Tom de Vries
2019-10-18 02:48:08 +02:00
parent 39849b0503
commit 85102364b2
96 changed files with 255 additions and 157 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
gdb/arm-tdep.c
View File

@ -3737,7 +3737,7 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
}
}
/* Push stack padding for dowubleword alignment. */
/* Push stack padding for doubleword alignment. */
if (nstack & (align - 1))
{
si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE);
@ -4828,7 +4828,7 @@ cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
if (dsc->u.branch.link)
{
/* The value of LR should be the next insn of current one. In order
not to confuse logic hanlding later insn `bx lr', if current insn mode
not to confuse logic handling later insn `bx lr', if current insn mode
is Thumb, the bit 0 of LR value should be set to 1. */
ULONGEST next_insn_addr = dsc->insn_addr + dsc->insn_size;
@ -5519,7 +5519,7 @@ install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
Before this sequence of instructions:
r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
r2 is the Rn value got from dispalced_read_reg.
r2 is the Rn value got from displaced_read_reg.
Insn1: push {pc} Write address of STR instruction + offset on stack
Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
@ -6196,7 +6196,7 @@ cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
}
/* Common copy routine for svc instruciton. */
/* Common copy routine for svc instruction. */
static int
install_svc (struct gdbarch *gdbarch, struct regcache *regs,
@ -9445,7 +9445,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
}
/* Add standard register aliases. We add aliases even for those
nanes which are used by the current architecture - it's simpler,
names which are used by the current architecture - it's simpler,
and does no harm, since nothing ever lists user registers. */
for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
user_reg_add (gdbarch, arm_register_aliases[i].name,
@ -10687,7 +10687,7 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
{
reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
/* LDR insn has a capability to do branching, if
MOV LR, PC is precedded by LDR insn having Rn as R15
MOV LR, PC is preceded by LDR insn having Rn as R15
in that case, it emulates branch and link insn, and hence we
need to save CSPR and PC as well. */
if (15 != reg_dest)
@ -13006,7 +13006,7 @@ class instruction_reader : public abstract_memory_reader
} // namespace
/* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
and positive val on fauilure. */
and positive val on failure. */
static int
extract_arm_insn (abstract_memory_reader& reader,