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RISC-V: re-arrange opcode table for consistent alias handling

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For disassembly to pick up aliases in favor of underlying insns (helping
readability in the common case), the aliases need to come ahead of the
"base" insns. Slightly more code movement is needed because of insns
with the same name needing to stay next to each other.

Note that the "rorw" alias entry also has the missing INSN_ALIAS added
here.

Clone a few testcases to exercise -Mno-aliases some more, better
covering the differences between the default and that disassembly mode.
This commit is contained in:
Jan Beulich
2022-09-30 10:19:00 +02:00
parent 79d635fc64
commit 839189bc93
28 changed files with 422 additions and 206 deletions
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2
ld/testsuite/ld-riscv-elf/ifunc-plt-01.d
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@ -11,7 +11,7 @@ Disassembly of section .text:
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|__DATA_BEGIN__.*|.*)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*

2
ld/testsuite/ld-riscv-elf/ifunc-plt-02.d
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@ -13,7 +13,7 @@ Disassembly of section .text:
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(__DATA_BEGIN__.*|.*)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*

2
ld/testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d
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@ -9,7 +9,7 @@ Disassembly of section .text:
#...
0+[0-9a-f]+ <bar>:
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+addi[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>
#...

4
ld/testsuite/ld-riscv-elf/pcgp-relax-02.d
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@ -10,6 +10,6 @@ Disassembly of section .text:
[0-9a-f]+ <_start>:
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+a1.*
.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a0,gp.*<data_a>
.*:[ ]+[0-9a-f]+[ ]+addi[ ]+a1,a1.*<data_b>
.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a0,gp.*<data_a>
.*:[ ]+[0-9a-f]+[ ]+addi?[ ]+a1,a1.*<data_b>
#pass

4
ld/testsuite/ld-riscv-elf/weakref32.d
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@ -9,12 +9,12 @@ Disassembly of section \.text:
90000004: 02078663 beqz a5,90000030 <_start\+0x30>
90000008: 00000793 li a5,0
9000000c: 02078263 beqz a5,90000030 <_start\+0x30>
90000010: ff010113 addi sp,sp,-16
90000010: ff010113 addi? sp,sp,-16
90000014: 00112623 sw ra,12\(sp\)
90000018: 00000097 auipc ra,0x0
9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000>
90000020: 00c12083 lw ra,12\(sp\)
90000024: 01010113 addi sp,sp,16
90000024: 01010113 addi? sp,sp,16
90000028: 00000317 auipc t1,0x0
9000002c: 00000067 jr zero # 0 <_start\-0x90000000>
90000030: 00008067 ret

4
ld/testsuite/ld-riscv-elf/weakref64.d
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@ -9,12 +9,12 @@ Disassembly of section \.text:
90000004: 02078663 beqz a5,90000030 <_start\+0x30>
90000008: 00000793 li a5,0
9000000c: 02078263 beqz a5,90000030 <_start\+0x30>
90000010: ff010113 addi sp,sp,-16
90000010: ff010113 addi? sp,sp,-16
90000014: 00113423 sd ra,8\(sp\)
90000018: 00000097 auipc ra,0x0
9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000>
90000020: 00813083 ld ra,8\(sp\)
90000024: 01010113 addi sp,sp,16
90000024: 01010113 addi? sp,sp,16
90000028: 00000317 auipc t1,0x0
9000002c: 00000067 jr zero # 0 <_start\-0x90000000>
90000030: 00008067 ret