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aarch64: Remove support for CSRE

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This patch removes support for the CSRE extension from aarch64
gas/objdump.
CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program
and at this time Arm is withdrawing this particular feature.

The patch removes the system registers and the CSR PDEC instruction.

gas/ChangeLog
	* NEWS: Remove CSRE.
	* config/tc-aarch64.c (parse_csr_operand): Delete.
	(parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR.
	(aarch64_features): Remove csre.
	* doc/c-aarch64.texi: Remove CSRE.
	* testsuite/gas/aarch64/csre.d: Delete.
	* testsuite/gas/aarch64/csre-invalid.s: Likewise.
	* testsuite/gas/aarch64/csre-invalid.d: Likewise.
	* testsuite/gas/aarch64/csre_csr.s: Likewise.
	* testsuite/gas/aarch64/csre_csr.d: Likewise.
	* testsuite/gas/aarch64/csre_csr-invalid.s: Likewise.
	* testsuite/gas/aarch64/csre_csr-invalid.l: Likewise.
	* testsuite/gas/aarch64/csre_csr-invalid.d: Likewise.

include/ChangeLog

	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete.
	(aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR.

opcodes/ChangeLog

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-opc.c (aarch64_print_operand): Delete handling of
	AARCH64_OPND_CSRE_CSR.
	* aarch64-tbl.h (aarch64_feature_csre): Delete.
	(CSRE): Likewise.
	(_CSRE_INSN): Likewise.
	(aarch64_opcode_table): Delete csr.
This commit is contained in:
Kyrylo Tkachov
2021-01-05 17:39:04 +00:00
parent c0f6e439cc
commit 82c70b08df
20 changed files with 1457 additions and 1535 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/opcode/aarch64.h
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@ -51,7 +51,6 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
@ -440,7 +439,6 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
};
/* Qualifier constrains an operand. It either specifies a variant of an