espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-22 19:09:31 +08:00
Code Issues Packages Projects Releases Wiki Activity

Add new opcodes

Browse Source
This commit is contained in:
Nick Clifton
2001-03-16 18:42:26 +00:00
parent 435b259cb0
commit 82b66b2339
3 changed files with 536 additions and 497 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2001-03-16 Martin Schwidefsky <schwidefsky@de.ibm.com>
* s390-opc.c: Add new opcodes. Smooth out formatting.
* s390-opc.txt: Add new opcodes.
2001-03-06 Nick Clifton <nickc@redhat.com>
* arm-dis.c (print_insn_thumb): Compute destination address

22
opcodes/s390-opc.c
View File

@ -276,7 +276,8 @@ const struct s390_operand s390_operands[] =
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
const struct s390_opcode s390_opformats[] = {
const struct s390_opcode s390_opformats[] =
{
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3 },
{ "ri", OP8(0x00LL), MASK_RI, INSTR_RI, 3 },
{ "ri_a", OP8(0x00LL), MASK_RI_A, INSTR_RI_A, 3 },
@ -363,7 +364,8 @@ const int s390_num_opformats =
The disassembler reads the table in order and prints the first
instruction which matches. */
const struct s390_opcode s390_opcodes[] = {
const struct s390_opcode s390_opcodes[] =
{
{ "dp", OP8(0xfdLL), MASK_SS_LL, INSTR_SS_LL, 3},
{ "mp", OP8(0xfcLL), MASK_SS_LL, INSTR_SS_LL, 3},
{ "sp", OP8(0xfbLL), MASK_SS_LL, INSTR_SS_LL, 3},
@ -405,6 +407,7 @@ const struct s390_opcode s390_opcodes[] = {
{ "brxlg", OP48(0xec0000000045LL), MASK_RIE_A, INSTR_RIE_A, 2},
{ "brxhg", OP48(0xec0000000044LL), MASK_RIE_A, INSTR_RIE_A, 2},
{ "lmh", OP48(0xeb0000000096LL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "mvclu", OP48(0xeb000000008eLL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "icmh", OP48(0xeb0000000080LL), MASK_RSE_M, INSTR_RSE_M, 2},
{ "bxleg", OP48(0xeb0000000045LL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "bxhg", OP48(0xeb0000000044LL), MASK_RSE_R, INSTR_RSE_R, 2},
@ -424,6 +427,8 @@ const struct s390_opcode s390_opcodes[] = {
{ "slag", OP48(0xeb000000000bLL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "srag", OP48(0xeb000000000aLL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "lmg", OP48(0xeb0000000004LL), MASK_RSE_R, INSTR_RSE_R, 2},
{ "unpka", OP8(0xeaLL), MASK_SS_L, INSTR_SS_L, 2},
{ "pka", OP8(0xe9LL), MASK_SS_L, INSTR_SS_L, 2},
{ "mvcin", OP8(0xe8LL), MASK_SS_L, INSTR_SS_L, 3},
{ "mvcdk", OP16(0xe50fLL), MASK_SSE, INSTR_SSE, 3},
{ "mvcsk", OP16(0xe50eLL), MASK_SSE, INSTR_SSE, 3},
@ -476,6 +481,8 @@ const struct s390_opcode s390_opcodes[] = {
{ "ag", OP48(0xe30000000008LL), MASK_RXE, INSTR_RXE, 2},
{ "lg", OP48(0xe30000000004LL), MASK_RXE, INSTR_RXE, 2},
{ "lrag", OP48(0xe30000000003LL), MASK_RXE, INSTR_RXE, 2},
{ "unpku", OP8(0xe2LL), MASK_SS_L, INSTR_SS_L, 2},
{ "pku", OP8(0xe1LL), MASK_SS_L, INSTR_SS_L, 2},
{ "edmk", OP8(0xdfLL), MASK_SS_L, INSTR_SS_L, 3},
{ "ed", OP8(0xdeLL), MASK_SS_L, INSTR_SS_L, 3},
{ "trt", OP8(0xddLL), MASK_SS_L, INSTR_SS_L, 3},
@ -527,6 +534,10 @@ const struct s390_opcode s390_opcodes[] = {
{ "alcgr", OP16(0xb988LL), MASK_RRE, INSTR_RRE, 2},
{ "dlgr", OP16(0xb987LL), MASK_RRE, INSTR_RRE, 2},
{ "mlgr", OP16(0xb986LL), MASK_RRE, INSTR_RRE, 2},
{ "troo", OP16(0xb993LL), MASK_RRE, INSTR_RRE, 2},
{ "trot", OP16(0xb992LL), MASK_RRE, INSTR_RRE, 2},
{ "trto", OP16(0xb991LL), MASK_RRE, INSTR_RRE, 2},
{ "trtt", OP16(0xb990LL), MASK_RRE, INSTR_RRE, 2},
{ "xgr", OP16(0xb982LL), MASK_RRE, INSTR_RRE, 2},
{ "ogr", OP16(0xb981LL), MASK_RRE, INSTR_RRE, 2},
{ "ngr", OP16(0xb980LL), MASK_RRE, INSTR_RRE, 2},
@ -586,10 +597,17 @@ const struct s390_opcode s390_opcodes[] = {
{ "cefbr", OP16(0xb394LL), MASK_RRE_F, INSTR_RRE_F, 3},
{ "efpc", OP16(0xb38cLL), MASK_RRE, INSTR_RRE, 3},
{ "sfpc", OP16(0xb384LL), MASK_RRE, INSTR_RRE, 3},
{ "lzxr", OP16(0xb376LL), MASK_RRE_R, INSTR_RRE_R, 2},
{ "lzdr", OP16(0xb375LL), MASK_RRE_R, INSTR_RRE_R, 2},
{ "lzer", OP16(0xb374LL), MASK_RRE_R, INSTR_RRE_R, 2},
{ "fidbr", OP16(0xb35fLL), MASK_RRF_M, INSTR_RRF_M, 3},
{ "didbr", OP16(0xb35bLL), MASK_RRF_RM, INSTR_RRF_RM, 3},
{ "thdr", OP16(0xb359LL), MASK_RRE, INSTR_RRE, 2},
{ "thder", OP16(0xb358LL), MASK_RRE, INSTR_RRE, 2},
{ "fiebr", OP16(0xb357LL), MASK_RRF_M, INSTR_RRF_M, 3},
{ "diebr", OP16(0xb353LL), MASK_RRF_RM, INSTR_RRF_RM, 3},
{ "tbdr", OP16(0xb351LL), MASK_RRF_M, INSTR_RRF_M, 2},
{ "tbedr", OP16(0xb350LL), MASK_RRF_M, INSTR_RRF_M, 2},
{ "dxbr", OP16(0xb34dLL), MASK_RRE_F, INSTR_RRE_F, 3},
{ "mxbr", OP16(0xb34cLL), MASK_RRE_F, INSTR_RRE_F, 3},
{ "sxbr", OP16(0xb34bLL), MASK_RRE_F, INSTR_RRE_F, 3},

16
opcodes/s390-opc.txt
View File

@ -599,3 +599,19 @@ eb000000001c rllg RSE_R "rotate left single logical 64" esame
eb000000001d rll RSE_R "rotate left single logical 32" esame
b278 stcke S "store clock extended" esame
b2a5 tre RRE "translate extended" esame
eb000000008e mvclu RSE_R "move long unicode" esame
e9 pka SS_L "pack ascii" esame
e1 pku SS_L "pack unicode" esame
b993 troo RRE "translate one to one" esame
b992 trot RRE "translate one to two" esame
b991 trto RRE "translate two to one" esame
b990 trtt RRE "translate two to two" esame
ea unpka SS_L "unpack ascii" esame
e2 unpku SS_L "unpack unicode" esame
b358 thder RRE "convert short bfp to long hfp" esame
b359 thdr RRE "convert long bfp to long hfp" esame
b350 tbedr RRF_M "convert long hfp to short bfp" esame
b351 tbdr RRF_M "convert long hfp to long bfp" esame
b374 lzer RRE_R "load short zero" esame
b375 lzdr RRE_R "load long zero" esame
b376 lzxr RRE_R "load extended zero" esame