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[Arm, 2/3] Add instruction SB for AArch32

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This patch is part of the patch series to add support for ARMv8.5-A
extensions.

(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.

*** include/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_EXT2_SB): New.
	(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.

*** opcodes/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (arm_opcodes): Add sb.
	(thumb32_opcodes): Likewise.

*** gas/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (arm_ext_sb): New.
	(insns): Add new sb instruction.
	(arm_extensions): Add "sb".
	* doc/c-arm.texi: Document the above.
	* testsuite/gas/arm/sb-bad.d: New test.
	* testsuite/gas/arm/sb-bad.l: New test.
	* testsuite/gas/arm/sb-thumb1.d: New test.
	* testsuite/gas/arm/sb-thumb2.d: New test.
	* testsuite/gas/arm/sb.s: New test.
	* testsuite/gas/arm/sb1.d: New test.
	* testsuite/gas/arm/sb2.d: New test.
This commit is contained in:
Sudakshina Das
2018-10-05 10:49:53 +01:00
committed by Richard Earnshaw
parent 23f233a595
commit 7fadb25d6f
14 changed files with 102 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
gas/ChangeLog
View File

@ -1,3 +1,17 @@
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_sb): New.
(insns): Add new sb instruction.
(arm_extensions): Add "sb".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/sb-bad.d: New test.
* testsuite/gas/arm/sb-bad.l: New test.
* testsuite/gas/arm/sb-thumb1.d: New test.
* testsuite/gas/arm/sb-thumb2.d: New test.
* testsuite/gas/arm/sb.s: New test.
* testsuite/gas/arm/sb1.d: New test.
* testsuite/gas/arm/sb2.d: New test.
2018-10-05 Sudakshina Das <sudi.das@arm.com> 2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_archs): New entry for armv8.5-a. * config/tc-arm.c (arm_archs): New entry for armv8.5-a.

12
gas/config/tc-arm.c
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@ -256,6 +256,8 @@ static const arm_feature_set arm_ext_v8_2 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
static const arm_feature_set arm_ext_v8_3 = static const arm_feature_set arm_ext_v8_3 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A); ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
static const arm_feature_set arm_ext_sb =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
static const arm_feature_set arm_arch_any = ARM_ANY; static const arm_feature_set arm_arch_any = ARM_ANY;
#ifdef OBJ_ELF #ifdef OBJ_ELF
@ -21516,6 +21518,13 @@ static const struct asm_opcode insns[] =
cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
/* ARMv8.5-A instructions. */
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_sb
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_sb
TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
/* ARMv8-M instructions. */ /* ARMv8-M instructions. */
#undef ARM_VARIANT #undef ARM_VARIANT
#define ARM_VARIANT NULL #define ARM_VARIANT NULL
@ -26418,6 +26427,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1, ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA), ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)), ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
ARM_ARCH_V8A),
ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),

2
gas/doc/c-arm.texi
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@ -189,6 +189,8 @@ The following extensions are currently supported:
@code{mp} (Multiprocessing Extensions for v7-A and v7-R @code{mp} (Multiprocessing Extensions for v7-A and v7-R
architectures), architectures),
@code{os} (Operating System for v6M architecture), @code{os} (Operating System for v6M architecture),
@code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
default from v8.5-A),
@code{sec} (Security Extensions for v6K and v7-A architectures), @code{sec} (Security Extensions for v6K and v7-A architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies @code{virt} (Virtualization Extensions for v7-A architecture, implies

5
gas/testsuite/gas/arm/sb-bad.d Normal file
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@ -0,0 +1,5 @@
# Check sb without +sb
#name: invalid sb instruction without +sb
#source: sb.s
#as: -march=armv8.2-a
#error_output: sb-bad.l

2
gas/testsuite/gas/arm/sb-bad.l Normal file
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@ -0,0 +1,2 @@
[^:]*: Assembler messages:
[^:]*:4: Error: selected processor does not support `sb' in ARM mode

11
gas/testsuite/gas/arm/sb-thumb1.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SB instruction (Thumb)
#source: sb.s
#as: -march=armv8.5-a -mthumb
# Test SB Instructio
.*: *file format .*arm.*
Disassembly of section .text:
.*> f3bf 8f70 sb

11
gas/testsuite/gas/arm/sb-thumb2.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SB instruction (Thumb) with +sb
#source: sb.s
#as: -march=armv8-a+sb -mthumb
# Test SB Instructio
.*: *file format .*arm.*
Disassembly of section .text:
.*> f3bf 8f70 sb

4
gas/testsuite/gas/arm/sb.s Normal file
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@ -0,0 +1,4 @@
@ Test case to validate SB
.section .text
.syntax unified
sb

11
gas/testsuite/gas/arm/sb1.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SB instruction
#source: sb.s
#as: -march=armv8.5-a
# Test SB Instructio
.*: *file format .*arm.*
Disassembly of section .text:
.*> f57ff070 sb

11
gas/testsuite/gas/arm/sb2.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SB instruction with +sb
#source: sb.s
#as: -march=armv8-a+sb
# Test SB Instructio
.*: *file format .*arm.*
Disassembly of section .text:
.*> f57ff070 sb

5
include/ChangeLog
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@ -1,3 +1,8 @@
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_SB): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
2018-10-05 Sudakshina Das <sudi.das@arm.com> 2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_V8_5A): New. * opcode/arm.h (ARM_EXT2_V8_5A): New.

4
include/opcode/arm.h
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@ -69,6 +69,7 @@
#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */ #define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */
#define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */ #define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */
#define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */ #define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */
#define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */
/* Co-processor space extensions. */ /* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@ -295,7 +296,8 @@
#define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \ #define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \
CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
| FPU_NEON_EXT_DOTPROD) | FPU_NEON_EXT_DOTPROD)
#define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_5A, \ #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, \
ARM_AEXT2_V8_5A | ARM_EXT2_SB, \
CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
| FPU_NEON_EXT_DOTPROD) | FPU_NEON_EXT_DOTPROD)
#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add sb.
(thumb32_opcodes): Likewise.
2018-10-05 Richard Henderson <rth@twiddle.net> 2018-10-05 Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com> Stafford Horne <shorne@gmail.com>

6
opcodes/arm-dis.c
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@ -1906,6 +1906,9 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
/* ARMv8.5-A instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
/* ARM V6K NOP hints. */ /* ARM V6K NOP hints. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f001, 0x0fffffff, "yield%c"}, 0x0320f001, 0x0fffffff, "yield%c"},
@ -2829,6 +2832,9 @@ static const struct opcode32 thumb32_opcodes[] =
/* Security extension instructions. */ /* Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
/* ARMv8.5-A instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
/* Instructions defined in the basic V6T2 set. */ /* Instructions defined in the basic V6T2 set. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},