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https://github.com/espressif/binutils-gdb.git
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Sanitization fixes.
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@ -475,6 +475,7 @@ can_make_parallel (a, b)
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m32r_insn * a;
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m32r_insn * a;
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m32r_insn * b;
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m32r_insn * b;
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{
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{
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/* start-sanitize-m32rx */
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PIPE_ATTR a_pipe;
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PIPE_ATTR a_pipe;
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PIPE_ATTR b_pipe;
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PIPE_ATTR b_pipe;
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@ -495,6 +496,7 @@ can_make_parallel (a, b)
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|| b_pipe == PIPE_O)
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|| b_pipe == PIPE_O)
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return "Instructions share the same execution pipeline";
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return "Instructions share the same execution pipeline";
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/* end-sanitize-m32rx */
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if ( writes_to_dest_reg (a->insn)
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if ( writes_to_dest_reg (a->insn)
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&& writes_to_dest_reg (b->insn)
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&& writes_to_dest_reg (b->insn)
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&& (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
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&& (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
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@ -561,7 +563,8 @@ assemble_parallel_insn (str, str2)
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as_bad (errmsg);
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as_bad (errmsg);
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return;
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return;
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}
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}
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/* start-sanitize-m32rx */
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/* Check to see if this is an allowable parallel insn. */
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/* Check to see if this is an allowable parallel insn. */
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if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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{
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@ -575,6 +578,7 @@ assemble_parallel_insn (str, str2)
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as_bad ("instruction '%s' is for the M32RX only", str);
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as_bad ("instruction '%s' is for the M32RX only", str);
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return;
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return;
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}
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}
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/* end-sanitize-m32rx */
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*str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
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*str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
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str3 = str; /* Save the original string pointer. */
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str3 = str; /* Save the original string pointer. */
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@ -592,6 +596,7 @@ assemble_parallel_insn (str, str2)
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return;
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return;
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}
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}
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/* start-sanitize-m32rx */
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/* Check it. */
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/* Check it. */
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if (! enable_m32rx
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if (! enable_m32rx
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&& CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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&& CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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@ -609,6 +614,7 @@ assemble_parallel_insn (str, str2)
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return;
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return;
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}
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}
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}
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}
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/* end-sanitize-m32rx */
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/* We assume that if the first instruction writes to a register that is
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/* We assume that if the first instruction writes to a register that is
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read by the second instruction it is because the programmer intended
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read by the second instruction it is because the programmer intended
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