espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-25 04:49:54 +08:00
Code Issues Packages Projects Releases Wiki Activity

MIPS16/opcodes: Free up `M' operand code

Browse Source 
The `M' and `m' MIPS16 operand codes are functionally the same, denoting
a 7-bit register list that is encoded the same way for both SAVE and
RESTORE.  Use `m' for both instructions then, making `M' available for a
different use.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
	(mips16_opcodes): Replace `M' with `m' for "restore".

	include/
	* opcode/mips.h: Remove `M' operand code.
This commit is contained in:
Maciej W. Rozycki
2018-02-20 20:51:36 +00:00
parent cd665a945e
commit 75f3166520
4 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* opcode/mips.h: Remove `M' operand code.
2018-02-12 Zebediah Figura <z.figura12@gmail.com> 2018-02-12 Zebediah Figura <z.figura12@gmail.com>
* coff/msdos.h: New header. * coff/msdos.h: New header.

5
include/opcode/mips.h
View File

@ -1889,13 +1889,12 @@ extern int bfd_mips_num_opcodes;
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
"m" 7 bit register list for save instruction (18 bit extended) "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended)
"M" 7 bit register list for restore instruction (18 bit extended)
Characters used so far, for quick reference when adding more: Characters used so far, for quick reference when adding more:
"0123456 89" "0123456 89"
".[]<>" ".[]<>"
"ABCDEFGHI KLMNOPQRSTUVWXYZ" "ABCDEFGHI KL NOPQRSTUVWXYZ"
"abcde ijklmnopqrs uvwxyz" "abcde ijklmnopqrs uvwxyz"
*/ */

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
(mips16_opcodes): Replace `M' with `m' for "restore".
2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Fix BXNS mask. * arm-dis.c (thumb_opcodes): Fix BXNS mask.

3
opcodes/mips16-opc.c
View File

@ -62,7 +62,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case 'G': SPECIAL (0, 0, REG28); case 'G': SPECIAL (0, 0, REG28);
case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST); case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
case 'M': SPECIAL (7, 0, SAVE_RESTORE_LIST);
case 'N': REG (5, 0, COPRO); case 'N': REG (5, 0, COPRO);
case 'O': UINT (3, 21); case 'O': UINT (3, 21);
case 'Q': REG (5, 16, HW); case 'Q': REG (5, 16, HW);
@ -445,7 +444,7 @@ const struct mips_opcode mips16_opcodes[] =
{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 },
{"xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 }, {"xori", "x,u", 0xf0006880, 0xf800f8e0, WR_1, 0, 0, E2, 0 },
/* MIPS16e additions; see above for compact jumps. */ /* MIPS16e additions; see above for compact jumps. */
{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 }, {"restore", "m", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 }, {"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
{"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 }, {"sdbbp", "", 0xe801, 0xffff, TRAP, SH, I32, 0, 0 },
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 }, {"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 },