espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-23 03:29:47 +08:00
Code Issues Packages Projects Releases Wiki Activity

sim: mn10300: migrate to standard uintXX_t types

Browse Source 
This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.
This commit is contained in:
Mike Frysinger
2021-12-05 12:28:57 -05:00
parent 436c3d9d7b
commit 74ccc97820
11 changed files with 498 additions and 505 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
sim/mn10300/am33-2.igen
View File

@ -98,7 +98,7 @@
"bset" "bset"
*am33_2 *am33_2
{ {
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -115,7 +115,7 @@
"bclr" "bclr"
*am33_2 *am33_2
{ {
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -1114,7 +1114,7 @@
else else
{ {
int reg = translate_rreg (SD_, Rm); int reg = translate_rreg (SD_, Rm);
unsigned32 val = State.regs[reg]; uint32_t val = State.regs[reg];
FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK)) FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
| ((FPCR & ~val) & EF_MASK); | ((FPCR & ~val) & EF_MASK);
} }
@ -1147,7 +1147,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK)) FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
| ((FPCR & ~val) & EF_MASK); | ((FPCR & ~val) & EF_MASK);
} }
@ -1424,7 +1424,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE); fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
} }
@ -1496,7 +1496,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_add (SD, CPU, cia, fpu_add (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE); &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@ -1569,7 +1569,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_sub (SD, CPU, cia, fpu_sub (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE); &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@ -1642,7 +1642,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_mul (SD, CPU, cia, fpu_mul (SD, CPU, cia,
&imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE); &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
@ -1715,7 +1715,7 @@
fpu_disabled_exception (SD, CPU, cia); fpu_disabled_exception (SD, CPU, cia);
else else
{ {
uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
fpu_div (SD, CPU, cia, fpu_div (SD, CPU, cia,
&XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE); &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);

580
sim/mn10300/am33.igen
View File

File diff suppressed because it is too large Load Diff

14
sim/mn10300/dv-mn103cpu.c
View File

@ -113,9 +113,9 @@ struct mn103cpu {
int pending_nmi; int pending_nmi;
int pending_reset; int pending_reset;
/* the visible registers */ /* the visible registers */
unsigned16 interrupt_vector[NR_VECTORS]; uint16_t interrupt_vector[NR_VECTORS];
unsigned16 internal_memory_control; uint16_t internal_memory_control;
unsigned16 cpu_mode; uint16_t cpu_mode;
}; };
@ -357,7 +357,7 @@ mn103cpu_io_read_buffer (struct hw *me,
unsigned nr_bytes) unsigned nr_bytes)
{ {
struct mn103cpu *controller = hw_data (me); struct mn103cpu *controller = hw_data (me);
unsigned16 val = 0; uint16_t val = 0;
enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base); enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base);
switch (reg) switch (reg)
@ -383,7 +383,7 @@ mn103cpu_io_read_buffer (struct hw *me,
} }
if (nr_bytes == 2) if (nr_bytes == 2)
*(unsigned16*) dest = H2LE_2 (val); *(uint16_t*) dest = H2LE_2 (val);
return nr_bytes; return nr_bytes;
} }
@ -396,14 +396,14 @@ mn103cpu_io_write_buffer (struct hw *me,
unsigned nr_bytes) unsigned nr_bytes)
{ {
struct mn103cpu *controller = hw_data (me); struct mn103cpu *controller = hw_data (me);
unsigned16 val; uint16_t val;
enum mn103cpu_regs reg; enum mn103cpu_regs reg;
if (nr_bytes != 2) if (nr_bytes != 2)
hw_abort (me, "must be two byte write"); hw_abort (me, "must be two byte write");
reg = decode_mn103cpu_addr (me, controller, base); reg = decode_mn103cpu_addr (me, controller, base);
val = LE2H_2 (* (unsigned16 *) source); val = LE2H_2 (* (uint16_t *) source);
switch (reg) switch (reg)
{ {

20
sim/mn10300/dv-mn103int.c
View File

@ -517,14 +517,14 @@ decode_group (struct hw *me,
return &controller->group[gid]; return &controller->group[gid];
} }
static unsigned8 static uint8_t
read_icr (struct hw *me, read_icr (struct hw *me,
struct mn103int *controller, struct mn103int *controller,
unsigned_word base) unsigned_word base)
{ {
unsigned_word offset; unsigned_word offset;
struct mn103int_group *group = decode_group (me, controller, base, &offset); struct mn103int_group *group = decode_group (me, controller, base, &offset);
unsigned8 val = 0; uint8_t val = 0;
switch (group->type) switch (group->type)
{ {
@ -571,7 +571,7 @@ static void
write_icr (struct hw *me, write_icr (struct hw *me,
struct mn103int *controller, struct mn103int *controller,
unsigned_word base, unsigned_word base,
unsigned8 val) uint8_t val)
{ {
unsigned_word offset; unsigned_word offset;
struct mn103int_group *group = decode_group (me, controller, base, &offset); struct mn103int_group *group = decode_group (me, controller, base, &offset);
@ -632,12 +632,12 @@ write_icr (struct hw *me,
/* Read the IAGR (Interrupt accepted group register) */ /* Read the IAGR (Interrupt accepted group register) */
static unsigned8 static uint8_t
read_iagr (struct hw *me, read_iagr (struct hw *me,
struct mn103int *controller, struct mn103int *controller,
unsigned_word offset) unsigned_word offset)
{ {
unsigned8 val; uint8_t val;
switch (offset) switch (offset)
{ {
case 0: case 0:
@ -687,13 +687,13 @@ external_group (struct mn103int *controller,
} }
} }
static unsigned8 static uint8_t
read_extmd (struct hw *me, read_extmd (struct hw *me,
struct mn103int *controller, struct mn103int *controller,
unsigned_word offset) unsigned_word offset)
{ {
int gid; int gid;
unsigned8 val = 0; uint8_t val = 0;
struct mn103int_group *group = external_group (controller, offset); struct mn103int_group *group = external_group (controller, offset);
if (group != NULL) if (group != NULL)
{ {
@ -710,7 +710,7 @@ static void
write_extmd (struct hw *me, write_extmd (struct hw *me,
struct mn103int *controller, struct mn103int *controller,
unsigned_word offset, unsigned_word offset,
unsigned8 val) uint8_t val)
{ {
int gid; int gid;
struct mn103int_group *group = external_group (controller, offset); struct mn103int_group *group = external_group (controller, offset);
@ -756,7 +756,7 @@ mn103int_io_read_buffer (struct hw *me,
unsigned nr_bytes) unsigned nr_bytes)
{ {
struct mn103int *controller = hw_data (me); struct mn103int *controller = hw_data (me);
unsigned8 *buf = dest; uint8_t *buf = dest;
unsigned byte; unsigned byte;
/* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */ /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++) for (byte = 0; byte < nr_bytes; byte++)
@ -789,7 +789,7 @@ mn103int_io_write_buffer (struct hw *me,
unsigned nr_bytes) unsigned nr_bytes)
{ {
struct mn103int *controller = hw_data (me); struct mn103int *controller = hw_data (me);
const unsigned8 *buf = source; const uint8_t *buf = source;
unsigned byte; unsigned byte;
/* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */ /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++) for (byte = 0; byte < nr_bytes; byte++)

24
sim/mn10300/dv-mn103iop.c
View File

@ -87,7 +87,7 @@ enum {
}; };
typedef struct _mn10300_ioport { typedef struct _mn10300_ioport {
unsigned8 output, output_mode, control, pin; uint8_t output, output_mode, control, pin;
struct hw_event *event; struct hw_event *event;
} mn10300_ioport; } mn10300_ioport;
@ -96,7 +96,7 @@ typedef struct _mn10300_ioport {
struct mn103iop { struct mn103iop {
struct mn103iop_block block[NR_BLOCKS]; struct mn103iop_block block[NR_BLOCKS];
mn10300_ioport port[NR_PORTS]; mn10300_ioport port[NR_PORTS];
unsigned8 p2ss, p4ss; uint8_t p2ss, p4ss;
}; };
@ -215,7 +215,7 @@ read_output_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = io_port->port[io_port_reg].output; *(uint8_t *)dest = io_port->port[io_port_reg].output;
} }
else else
{ {
@ -236,7 +236,7 @@ read_output_mode_reg (struct hw *me,
{ {
/* check if there are fields which can't be written and /* check if there are fields which can't be written and
take appropriate action depending what bits are set */ take appropriate action depending what bits are set */
*(unsigned8 *)dest = io_port->port[io_port_reg].output_mode; *(uint8_t *)dest = io_port->port[io_port_reg].output_mode;
} }
else else
{ {
@ -255,7 +255,7 @@ read_control_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = io_port->port[io_port_reg].control; *(uint8_t *)dest = io_port->port[io_port_reg].control;
} }
else else
{ {
@ -274,7 +274,7 @@ read_pin_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = io_port->port[io_port_reg].pin; *(uint8_t *)dest = io_port->port[io_port_reg].pin;
} }
else else
{ {
@ -296,11 +296,11 @@ read_dedicated_control_reg (struct hw *me,
/* select on io_port_reg: */ /* select on io_port_reg: */
if ( io_port_reg == P2SS ) if ( io_port_reg == P2SS )
{ {
*(unsigned8 *)dest = io_port->p2ss; *(uint8_t *)dest = io_port->p2ss;
} }
else else
{ {
*(unsigned8 *)dest = io_port->p4ss; *(uint8_t *)dest = io_port->p4ss;
} }
} }
else else
@ -375,7 +375,7 @@ write_output_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 buf = *(unsigned8 *)source; uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
if ( io_port_reg == 3 && (buf & 0xfc) != 0 ) if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@ -402,7 +402,7 @@ write_output_mode_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 buf = *(unsigned8 *)source; uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
/* check if there are fields which can't be written and /* check if there are fields which can't be written and
@ -432,7 +432,7 @@ write_control_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 buf = *(unsigned8 *)source; uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
if ( io_port_reg == 3 && (buf & 0xfc) != 0 ) if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@ -459,7 +459,7 @@ write_dedicated_control_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 buf = *(unsigned8 *)source; uint8_t buf = *(uint8_t *)source;
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
/* select on io_port_reg: */ /* select on io_port_reg: */

42
sim/mn10300/dv-mn103ser.c
View File

@ -81,8 +81,8 @@ enum serial_register_types {
#define SIO_STAT_RRDY 0x0010 #define SIO_STAT_RRDY 0x0010
typedef struct _mn10300_serial { typedef struct _mn10300_serial {
unsigned16 status, control; uint16_t status, control;
unsigned8 txb, rxb, intmode; uint8_t txb, rxb, intmode;
struct hw_event *event; struct hw_event *event;
} mn10300_serial; } mn10300_serial;
@ -91,7 +91,7 @@ typedef struct _mn10300_serial {
struct mn103ser { struct mn103ser {
struct mn103ser_block block; struct mn103ser_block block;
mn10300_serial device[NR_SERIAL_DEVS]; mn10300_serial device[NR_SERIAL_DEVS];
unsigned8 serial2_timer_reg; uint8_t serial2_timer_reg;
do_hw_poll_read_method *reader; do_hw_poll_read_method *reader;
}; };
@ -294,7 +294,7 @@ read_control_reg (struct hw *me,
/* really allow 1 byte read, too */ /* really allow 1 byte read, too */
if ( nr_bytes == 2 ) if ( nr_bytes == 2 )
{ {
*(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].control); *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].control);
} }
else else
{ {
@ -313,7 +313,7 @@ read_intmode_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = serial->device[serial_reg].intmode; *(uint8_t *)dest = serial->device[serial_reg].intmode;
} }
else else
{ {
@ -332,7 +332,7 @@ read_txb (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = serial->device[serial_reg].txb; *(uint8_t *)dest = serial->device[serial_reg].txb;
} }
else else
{ {
@ -351,7 +351,7 @@ read_rxb (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = serial->device[serial_reg].rxb; *(uint8_t *)dest = serial->device[serial_reg].rxb;
/* Reception buffer is now empty. */ /* Reception buffer is now empty. */
serial->device[serial_reg].status &= ~SIO_STAT_RRDY; serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
} }
@ -429,11 +429,11 @@ read_status_reg (struct hw *me,
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
*(unsigned8 *)dest = (unsigned8)serial->device[serial_reg].status; *(uint8_t *)dest = (uint8_t)serial->device[serial_reg].status;
} }
else if ( nr_bytes == 2 && serial_reg != SC2STR ) else if ( nr_bytes == 2 && serial_reg != SC2STR )
{ {
*(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].status); *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].status);
} }
else else
{ {
@ -451,7 +451,7 @@ read_serial2_timer_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
* (unsigned8 *) dest = (unsigned8) serial->serial2_timer_reg; * (uint8_t *) dest = (uint8_t) serial->serial2_timer_reg;
} }
else else
{ {
@ -480,7 +480,7 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2CTR: case SC2CTR:
read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes); read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR, HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
*(unsigned8 *)dest)); *(uint8_t *)dest));
break; break;
/* interrupt mode registers */ /* interrupt mode registers */
@ -489,7 +489,7 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2ICR: case SC2ICR:
read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes); read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR, HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
*(unsigned8 *)dest)); *(uint8_t *)dest));
break; break;
/* transmission buffers */ /* transmission buffers */
@ -516,12 +516,12 @@ mn103ser_io_read_buffer (struct hw *me,
case SC2STR: case SC2STR:
read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes); read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR, HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
*(unsigned8 *)dest)); *(uint8_t *)dest));
break; break;
case SC2TIM: case SC2TIM:
read_serial2_timer_reg(me, serial, dest, nr_bytes); read_serial2_timer_reg(me, serial, dest, nr_bytes);
HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest)); HW_TRACE ((me, "read - serial2 timer reg %d\n", *(uint8_t *)dest));
break; break;
default: default:
@ -539,7 +539,7 @@ write_control_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned16 val = LE2H_2 (*(unsigned16 *)source); uint16_t val = LE2H_2 (*(uint16_t *)source);
/* really allow 1 byte write, too */ /* really allow 1 byte write, too */
if ( nr_bytes == 2 ) if ( nr_bytes == 2 )
@ -568,7 +568,7 @@ write_intmode_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 val = *(unsigned8 *)source; uint8_t val = *(uint8_t *)source;
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
@ -604,7 +604,7 @@ write_txb (struct hw *me,
SIM_DESC sd = hw_system (me); SIM_DESC sd = hw_system (me);
int status; int status;
serial->device[serial_reg].txb = *(unsigned8 *)source; serial->device[serial_reg].txb = *(uint8_t *)source;
status = dv_sockser_status (sd); status = dv_sockser_status (sd);
if (!(status & DV_SOCKSER_DISCONNECTED)) if (!(status & DV_SOCKSER_DISCONNECTED))
@ -635,7 +635,7 @@ write_serial2_timer_reg (struct hw *me,
{ {
if ( nr_bytes == 1 ) if ( nr_bytes == 1 )
{ {
serial->serial2_timer_reg = *(unsigned8 *)source; serial->serial2_timer_reg = *(uint8_t *)source;
} }
else else
{ {
@ -663,7 +663,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC1CTR: case SC1CTR:
case SC2CTR: case SC2CTR:
HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n", HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n",
serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes)); serial_reg-SC0CTR, *(uint8_t *)source, nr_bytes));
write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes); write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes);
break; break;
@ -672,7 +672,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC1ICR: case SC1ICR:
case SC2ICR: case SC2ICR:
HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n", HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n",
serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes)); serial_reg-SC0ICR, *(uint8_t *)source, nr_bytes));
write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes); write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes);
break; break;
@ -701,7 +701,7 @@ mn103ser_io_write_buffer (struct hw *me,
case SC2TIM: case SC2TIM:
HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n", HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n",
*(unsigned8 *)source, nr_bytes)); *(uint8_t *)source, nr_bytes));
write_serial2_timer_reg(me, serial, source, nr_bytes); write_serial2_timer_reg(me, serial, source, nr_bytes);
break; break;

94
sim/mn10300/dv-mn103tim.c
View File

@ -97,12 +97,12 @@ enum timer_register_types {
#define NR_TIMERS 7 #define NR_TIMERS 7
typedef struct _mn10300_timer_regs { typedef struct _mn10300_timer_regs {
unsigned32 base; uint32_t base;
unsigned8 mode; uint8_t mode;
} mn10300_timer_regs; } mn10300_timer_regs;
typedef struct _mn10300_timer { typedef struct _mn10300_timer {
unsigned32 div_ratio, start; uint32_t div_ratio, start;
struct hw_event *event; struct hw_event *event;
} mn10300_timer; } mn10300_timer;
@ -113,8 +113,8 @@ struct mn103tim {
mn10300_timer timer[NR_TIMERS]; mn10300_timer timer[NR_TIMERS];
/* treat timer 6 registers specially. */ /* treat timer 6 registers specially. */
unsigned16 tm6md0, tm6md1, tm6bc, tm6ca, tm6cb; uint16_t tm6md0, tm6md1, tm6bc, tm6ca, tm6cb;
unsigned8 tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */ uint8_t tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */
}; };
/* output port ID's */ /* output port ID's */
@ -287,8 +287,8 @@ read_mode_reg (struct hw *me,
void *dest, void *dest,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned16 val16; uint16_t val16;
unsigned32 val32; uint32_t val32;
switch ( nr_bytes ) switch ( nr_bytes )
{ {
@ -296,24 +296,24 @@ read_mode_reg (struct hw *me,
/* Accessing 1 byte is ok for all mode registers. */ /* Accessing 1 byte is ok for all mode registers. */
if ( timer_nr == 6 ) if ( timer_nr == 6 )
{ {
*(unsigned8*)dest = timers->tm6md0; *(uint8_t*)dest = timers->tm6md0;
} }
else else
{ {
*(unsigned8*)dest = timers->reg[timer_nr].mode; *(uint8_t*)dest = timers->reg[timer_nr].mode;
} }
break; break;
case 2: case 2:
if ( timer_nr == 6 ) if ( timer_nr == 6 )
{ {
*(unsigned16 *)dest = (timers->tm6md0 << 8) | timers->tm6md1; *(uint16_t *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
} }
else if ( timer_nr == 0 || timer_nr == 2 ) else if ( timer_nr == 0 || timer_nr == 2 )
{ {
val16 = (timers->reg[timer_nr].mode << 8) val16 = (timers->reg[timer_nr].mode << 8)
| timers->reg[timer_nr+1].mode; | timers->reg[timer_nr+1].mode;
*(unsigned16*)dest = val16; *(uint16_t*)dest = val16;
} }
else else
{ {
@ -328,7 +328,7 @@ read_mode_reg (struct hw *me,
| (timers->reg[1].mode << 16) | (timers->reg[1].mode << 16)
| (timers->reg[2].mode << 8) | (timers->reg[2].mode << 8)
| timers->reg[3].mode; | timers->reg[3].mode;
*(unsigned32*)dest = val32; *(uint32_t*)dest = val32;
} }
else else
{ {
@ -350,8 +350,8 @@ read_base_reg (struct hw *me,
void *dest, void *dest,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned16 val16; uint16_t val16;
unsigned32 val32; uint32_t val32;
/* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */ /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
switch ( nr_bytes ) switch ( nr_bytes )
@ -360,7 +360,7 @@ read_base_reg (struct hw *me,
/* Reading 1 byte is ok for all registers. */ /* Reading 1 byte is ok for all registers. */
if ( timer_nr < NR_8BIT_TIMERS ) if ( timer_nr < NR_8BIT_TIMERS )
{ {
*(unsigned8*)dest = timers->reg[timer_nr].base; *(uint8_t*)dest = timers->reg[timer_nr].base;
} }
break; break;
@ -380,7 +380,7 @@ read_base_reg (struct hw *me,
{ {
val16 = timers->reg[timer_nr].base; val16 = timers->reg[timer_nr].base;
} }
*(unsigned16*)dest = val16; *(uint16_t*)dest = val16;
} }
break; break;
@ -389,12 +389,12 @@ read_base_reg (struct hw *me,
{ {
val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16) val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
| (timers->reg[2].base << 8) | timers->reg[3].base; | (timers->reg[2].base << 8) | timers->reg[3].base;
*(unsigned32*)dest = val32; *(uint32_t*)dest = val32;
} }
else if ( timer_nr == 4 ) else if ( timer_nr == 4 )
{ {
val32 = (timers->reg[4].base << 16) | timers->reg[5].base; val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
*(unsigned32*)dest = val32; *(uint32_t*)dest = val32;
} }
else else
{ {
@ -416,7 +416,7 @@ read_counter (struct hw *me,
void *dest, void *dest,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned32 val; uint32_t val;
if ( NULL == timers->timer[timer_nr].event ) if ( NULL == timers->timer[timer_nr].event )
{ {
@ -449,15 +449,15 @@ read_counter (struct hw *me,
switch (nr_bytes) { switch (nr_bytes) {
case 1: case 1:
*(unsigned8 *)dest = val; *(uint8_t *)dest = val;
break; break;
case 2: case 2:
*(unsigned16 *)dest = val; *(uint16_t *)dest = val;
break; break;
case 4: case 4:
*(unsigned32 *)dest = val; *(uint32_t *)dest = val;
break; break;
default: default:
@ -474,26 +474,26 @@ read_special_timer6_reg (struct hw *me,
void *dest, void *dest,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned32 val; uint32_t val;
switch (nr_bytes) { switch (nr_bytes) {
case 1: case 1:
{ {
switch ( timer_nr ) { switch ( timer_nr ) {
case TM6MDA: case TM6MDA:
*(unsigned8 *)dest = timers->tm6mda; *(uint8_t *)dest = timers->tm6mda;
break; break;
case TM6MDB: case TM6MDB:
*(unsigned8 *)dest = timers->tm6mdb; *(uint8_t *)dest = timers->tm6mdb;
break; break;
case TM6CA: case TM6CA:
*(unsigned8 *)dest = timers->tm6ca; *(uint8_t *)dest = timers->tm6ca;
break; break;
case TM6CB: case TM6CB:
*(unsigned8 *)dest = timers->tm6cb; *(uint8_t *)dest = timers->tm6cb;
break; break;
default: default:
@ -505,11 +505,11 @@ read_special_timer6_reg (struct hw *me,
case 2: case 2:
if ( timer_nr == TM6CA ) if ( timer_nr == TM6CA )
{ {
*(unsigned16 *)dest = timers->tm6ca; *(uint16_t *)dest = timers->tm6ca;
} }
else if ( timer_nr == TM6CB ) else if ( timer_nr == TM6CB )
{ {
*(unsigned16 *)dest = timers->tm6cb; *(uint16_t *)dest = timers->tm6cb;
} }
else else
{ {
@ -642,8 +642,8 @@ write_base_reg (struct hw *me,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned i; unsigned i;
const unsigned8 *buf8 = source; const uint8_t *buf8 = source;
const unsigned16 *buf16 = source; const uint16_t *buf16 = source;
/* If TMnCNE == 0 (counting is off), writing to the base register /* If TMnCNE == 0 (counting is off), writing to the base register
(TMnBR) causes a simultaneous write to the counter reg (TMnBC). (TMnBR) causes a simultaneous write to the counter reg (TMnBC).
@ -713,8 +713,8 @@ write_mode_reg (struct hw *me,
/* for timers 0 to 5 */ /* for timers 0 to 5 */
{ {
unsigned i; unsigned i;
unsigned8 mode_val, next_mode_val; uint8_t mode_val, next_mode_val;
unsigned32 div_ratio; uint32_t div_ratio;
if ( nr_bytes != 1 ) if ( nr_bytes != 1 )
{ {
@ -722,7 +722,7 @@ write_mode_reg (struct hw *me,
timer_nr); timer_nr);
} }
mode_val = *(unsigned8 *)source; mode_val = *(uint8_t *)source;
timers->reg[timer_nr].mode = mode_val; timers->reg[timer_nr].mode = mode_val;
if ( ( mode_val & count_and_load_mask ) == count_and_load_mask ) if ( ( mode_val & count_and_load_mask ) == count_and_load_mask )
@ -840,8 +840,8 @@ write_tm6md (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned8 mode_val0 = 0x00, mode_val1 = 0x00; uint8_t mode_val0 = 0x00, mode_val1 = 0x00;
unsigned32 div_ratio; uint32_t div_ratio;
long timer_nr = 6; long timer_nr = 6;
unsigned_word offset = address - timers->block[0].base; unsigned_word offset = address - timers->block[0].base;
@ -854,7 +854,7 @@ write_tm6md (struct hw *me,
if ( offset == 0x84 ) /* address of TM6MD */ if ( offset == 0x84 ) /* address of TM6MD */
{ {
/* Fill in first byte of mode */ /* Fill in first byte of mode */
mode_val0 = *(unsigned8 *)source; mode_val0 = *(uint8_t *)source;
timers->tm6md0 = mode_val0; timers->tm6md0 = mode_val0;
if ( ( mode_val0 & 0x26 ) != 0 ) if ( ( mode_val0 & 0x26 ) != 0 )
@ -868,11 +868,11 @@ write_tm6md (struct hw *me,
/* Fill in second byte of mode */ /* Fill in second byte of mode */
if ( nr_bytes == 2 ) if ( nr_bytes == 2 )
{ {
mode_val1 = *(unsigned8 *)source+1; mode_val1 = *(uint8_t *)source+1;
} }
else else
{ {
mode_val1 = *(unsigned8 *)source; mode_val1 = *(uint8_t *)source;
} }
timers->tm6md1 = mode_val1; timers->tm6md1 = mode_val1;
@ -931,26 +931,26 @@ write_special_timer6_reg (struct hw *me,
const void *source, const void *source,
unsigned nr_bytes) unsigned nr_bytes)
{ {
unsigned32 val; uint32_t val;
switch (nr_bytes) { switch (nr_bytes) {
case 1: case 1:
{ {
switch ( timer_nr ) { switch ( timer_nr ) {
case TM6MDA: case TM6MDA:
timers->tm6mda = *(unsigned8 *)source; timers->tm6mda = *(uint8_t *)source;
break; break;
case TM6MDB: case TM6MDB:
timers->tm6mdb = *(unsigned8 *)source; timers->tm6mdb = *(uint8_t *)source;
break; break;
case TM6CA: case TM6CA:
timers->tm6ca = *(unsigned8 *)source; timers->tm6ca = *(uint8_t *)source;
break; break;
case TM6CB: case TM6CB:
timers->tm6cb = *(unsigned8 *)source; timers->tm6cb = *(uint8_t *)source;
break; break;
default: default:
@ -962,11 +962,11 @@ write_special_timer6_reg (struct hw *me,
case 2: case 2:
if ( timer_nr == TM6CA ) if ( timer_nr == TM6CA )
{ {
timers->tm6ca = *(unsigned16 *)source; timers->tm6ca = *(uint16_t *)source;
} }
else if ( timer_nr == TM6CB ) else if ( timer_nr == TM6CB )
{ {
timers->tm6cb = *(unsigned16 *)source; timers->tm6cb = *(uint16_t *)source;
} }
else else
{ {
@ -992,7 +992,7 @@ mn103tim_io_write_buffer (struct hw *me,
enum timer_register_types timer_reg; enum timer_register_types timer_reg;
HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base, HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
(int) nr_bytes, *(unsigned32 *)source)); (int) nr_bytes, *(uint32_t *)source));
timer_reg = decode_addr (me, timers, base); timer_reg = decode_addr (me, timers, base);

6
sim/mn10300/interp.c
View File

@ -320,7 +320,7 @@ sim_create_inferior (SIM_DESC sd,
} else { } else {
PC = 0; PC = 0;
} }
CPU_PC_SET (STATE_CPU (sd, 0), (unsigned64) PC); CPU_PC_SET (STATE_CPU (sd, 0), (uint64_t) PC);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2) if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
PSW |= PSW_FE; PSW |= PSW_FE;
@ -335,7 +335,7 @@ static int
mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{ {
reg_t reg = State.regs[rn]; reg_t reg = State.regs[rn];
uint8 *a = memory; uint8_t *a = memory;
a[0] = reg; a[0] = reg;
a[1] = reg >> 8; a[1] = reg >> 8;
a[2] = reg >> 16; a[2] = reg >> 16;
@ -346,7 +346,7 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
static int static int
mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{ {
uint8 *a = memory; uint8_t *a = memory;
State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0]; State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0];
return length; return length;
} }

152
sim/mn10300/mn10300.igen
View File

@ -21,7 +21,7 @@
*am33_2 *am33_2
{ {
/* OP_8000 (); */ /* OP_8000 (); */
signed32 immed = EXTEND8 (IMM8); int32_t immed = EXTEND8 (IMM8);
State.regs[REG_D0+DN0] = immed; State.regs[REG_D0+DN0] = immed;
PC = cia; PC = cia;
} }
@ -776,7 +776,7 @@
{ {
/* OP_2C0000 (); */ /* OP_2C0000 (); */
unsigned32 value; uint32_t value;
PC = cia; PC = cia;
value = EXTEND16 (FETCH16(IMM16A, IMM16B)); value = EXTEND16 (FETCH16(IMM16A, IMM16B));
@ -794,7 +794,7 @@
{ {
/* OP_FCCC0000 (); */ /* OP_FCCC0000 (); */
unsigned32 value; uint32_t value;
PC = cia; PC = cia;
value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@ -812,7 +812,7 @@
{ {
/* OP_240000 (); */ /* OP_240000 (); */
unsigned32 value; uint32_t value;
PC = cia; PC = cia;
value = FETCH16(IMM16A, IMM16B); value = FETCH16(IMM16A, IMM16B);
@ -1734,7 +1734,7 @@
{ {
/* OP_F8FE00 (); */ /* OP_F8FE00 (); */
unsigned32 imm; uint32_t imm;
/* Note: no PSW changes. */ /* Note: no PSW changes. */
PC = cia; PC = cia;
@ -1753,7 +1753,7 @@
{ {
/* OP_FAFE0000 (); */ /* OP_FAFE0000 (); */
unsigned32 imm; uint32_t imm;
/* Note: no PSW changes. */ /* Note: no PSW changes. */
PC = cia; PC = cia;
@ -1772,7 +1772,7 @@
{ {
/* OP_FCFE0000 (); */ /* OP_FCFE0000 (); */
unsigned32 imm; uint32_t imm;
/* Note: no PSW changes. */ /* Note: no PSW changes. */
PC = cia; PC = cia;
@ -1792,7 +1792,7 @@
{ {
/* OP_F140 (); */ /* OP_F140 (); */
int z, c, n, v; int z, c, n, v;
unsigned32 reg1, reg2, sum; uint32_t reg1, reg2, sum;
PC = cia; PC = cia;
reg1 = State.regs[REG_D0 + DM1]; reg1 = State.regs[REG_D0 + DM1];
@ -1912,7 +1912,7 @@
{ {
/* OP_F180 (); */ /* OP_F180 (); */
int z, c, n, v; int z, c, n, v;
unsigned32 reg1, reg2, difference; uint32_t reg1, reg2, difference;
PC = cia; PC = cia;
reg1 = State.regs[REG_D0 + DM1]; reg1 = State.regs[REG_D0 + DM1];
@ -1942,12 +1942,12 @@
{ {
/* OP_F240 (); */ /* OP_F240 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
* (signed64)(signed32)State.regs[REG_D0 + DM1]); * (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -1967,12 +1967,12 @@
{ {
/* OP_F250 (); */ /* OP_F250 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0] temp = ((uint64_t)State.regs[REG_D0 + DN0]
* (unsigned64)State.regs[REG_D0 + DM1]); * (uint64_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -1992,20 +1992,20 @@
{ {
/* OP_F260 (); */ /* OP_F260 (); */
signed64 temp; int64_t temp;
signed32 denom; int32_t denom;
int n, z, v; int n, z, v;
PC = cia; PC = cia;
denom = (signed32)State.regs[REG_D0 + DM1]; denom = (int32_t)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR]; temp = State.regs[REG_MDR];
temp <<= 32; temp <<= 32;
temp |= State.regs[REG_D0 + DN0]; temp |= State.regs[REG_D0 + DN0];
if ( !(v = (0 == denom)) ) if ( !(v = (0 == denom)) )
{ {
State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1]; State.regs[REG_MDR] = temp % (int32_t)State.regs[REG_D0 + DM1];
temp /= (signed32)State.regs[REG_D0 + DM1]; temp /= (int32_t)State.regs[REG_D0 + DM1];
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
} }
else else
@ -2030,12 +2030,12 @@
{ {
/* OP_F270 (); */ /* OP_F270 (); */
unsigned64 temp; uint64_t temp;
unsigned32 denom; uint32_t denom;
int n, z, v; int n, z, v;
PC = cia; PC = cia;
denom = (unsigned32)State.regs[REG_D0 + DM1]; denom = (uint32_t)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR]; temp = State.regs[REG_MDR];
temp <<= 32; temp <<= 32;
temp |= State.regs[REG_D0 + DN0]; temp |= State.regs[REG_D0 + DN0];
@ -2067,7 +2067,7 @@
{ {
/* OP_40 (); */ /* OP_40 (); */
unsigned32 imm; uint32_t imm;
PC = cia; PC = cia;
imm = 1; imm = 1;
@ -2591,7 +2591,7 @@
{ {
/* OP_F080 (); */ /* OP_F080 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2615,7 +2615,7 @@
{ {
/* OP_FE000000 (); */ /* OP_FE000000 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2639,7 +2639,7 @@
{ {
/* OP_FAF00000 (); */ /* OP_FAF00000 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2662,7 +2662,7 @@
{ {
/* OP_F090 (); */ /* OP_F090 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2686,7 +2686,7 @@
{ {
/* OP_FE010000 (); */ /* OP_FE010000 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2710,7 +2710,7 @@
{ {
/* OP_FAF40000 (); */ /* OP_FAF40000 (); */
unsigned32 temp; uint32_t temp;
int z; int z;
PC = cia; PC = cia;
@ -2733,7 +2733,7 @@
{ {
/* OP_F2B0 (); */ /* OP_F2B0 (); */
signed32 temp; int32_t temp;
int z, n, c; int z, n, c;
PC = cia; PC = cia;
@ -2758,7 +2758,7 @@
{ {
/* OP_F8C800 (); */ /* OP_F8C800 (); */
signed32 temp; int32_t temp;
int z, n, c; int z, n, c;
PC = cia; PC = cia;
@ -2892,7 +2892,7 @@
{ {
/* OP_F284 (); */ /* OP_F284 (); */
unsigned32 value; uint32_t value;
int c,n,z; int c,n,z;
PC = cia; PC = cia;
@ -2919,7 +2919,7 @@
{ {
/* OP_F280 (); */ /* OP_F280 (); */
unsigned32 value; uint32_t value;
int c,n,z; int c,n,z;
PC = cia; PC = cia;
@ -3499,7 +3499,7 @@
{ {
/* OP_F0F0 (); */ /* OP_F0F0 (); */
unsigned32 next_pc, sp; uint32_t next_pc, sp;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -3521,7 +3521,7 @@
{ {
/* OP_FAFF0000 (); */ /* OP_FAFF0000 (); */
unsigned32 next_pc, sp; uint32_t next_pc, sp;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -3543,7 +3543,7 @@
{ {
/* OP_FCFF0000 (); */ /* OP_FCFF0000 (); */
unsigned32 next_pc, sp; uint32_t next_pc, sp;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -3565,7 +3565,7 @@
{ {
/* OP_F0FC (); */ /* OP_F0FC (); */
unsigned32 sp; uint32_t sp;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
State.regs[REG_PC] = load_word(sp); State.regs[REG_PC] = load_word(sp);
@ -3583,7 +3583,7 @@
{ {
/* OP_F0FD (); */ /* OP_F0FD (); */
unsigned32 sp; uint32_t sp;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
PSW = load_half(sp); PSW = load_half(sp);
@ -3603,7 +3603,7 @@
{ {
/* OP_F0FE (); */ /* OP_F0FE (); */
unsigned32 sp, next_pc; uint32_t sp, next_pc;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -3685,12 +3685,12 @@
{ {
/* OP_F600 (); */ /* OP_F600 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
* (signed64)(signed32)State.regs[REG_D0 + DM1]); * (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3710,12 +3710,12 @@
{ {
/* OP_F90000 (); */ /* OP_F90000 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
* (signed64)(signed32)EXTEND8 (IMM8)); * (int64_t)(int32_t)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3735,12 +3735,12 @@
{ {
/* OP_FB000000 (); */ /* OP_FB000000 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
* (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B))); * (int64_t)(int32_t)EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3760,12 +3760,12 @@
{ {
/* OP_FD000000 (); */ /* OP_FD000000 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0] temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
* (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); * (int64_t)(int32_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3785,12 +3785,12 @@
{ {
/* OP_F610 (); */ /* OP_F610 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((unsigned64) State.regs[REG_D0 + DN0] temp = ((uint64_t) State.regs[REG_D0 + DN0]
* (unsigned64) State.regs[REG_D0 + DM1]); * (uint64_t) State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3810,12 +3810,12 @@
{ {
/* OP_F91400 (); */ /* OP_F91400 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0] temp = ((uint64_t)State.regs[REG_D0 + DN0]
* (unsigned64)EXTEND8 (IMM8)); * (uint64_t)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3835,12 +3835,12 @@
{ {
/* OP_FB140000 (); */ /* OP_FB140000 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0] temp = ((uint64_t)State.regs[REG_D0 + DN0]
* (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B))); * (uint64_t) EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3860,12 +3860,12 @@
{ {
/* OP_FD140000 (); */ /* OP_FD140000 (); */
unsigned64 temp; uint64_t temp;
int n, z; int n, z;
PC = cia; PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0] temp = ((uint64_t)State.regs[REG_D0 + DN0]
* (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D))); * (uint64_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff; State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0); z = (State.regs[REG_D0 + DN0] == 0);
@ -3975,8 +3975,8 @@
{ {
/* OP_CE00 (); */ /* OP_CE00 (); */
unsigned32 sp = State.regs[REG_SP]; uint32_t sp = State.regs[REG_SP];
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
mask = REGS; mask = REGS;
@ -4074,8 +4074,8 @@
{ {
/* OP_CF00 (); */ /* OP_CF00 (); */
unsigned32 sp = State.regs[REG_SP]; uint32_t sp = State.regs[REG_SP];
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
mask = REGS; mask = REGS;
@ -4173,8 +4173,8 @@
{ {
/* OP_CD000000 (); */ /* OP_CD000000 (); */
unsigned32 next_pc, sp; uint32_t next_pc, sp;
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -4282,8 +4282,8 @@
{ {
/* OP_DD000000 (); */ /* OP_DD000000 (); */
unsigned32 next_pc, sp; uint32_t next_pc, sp;
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
sp = State.regs[REG_SP]; sp = State.regs[REG_SP];
@ -4391,8 +4391,8 @@
{ {
/* OP_DF0000 (); */ /* OP_DF0000 (); */
unsigned32 sp, offset; uint32_t sp, offset;
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
State.regs[REG_SP] += IMM8; State.regs[REG_SP] += IMM8;
@ -4496,8 +4496,8 @@
{ {
/* OP_DE0000 (); */ /* OP_DE0000 (); */
unsigned32 sp, offset; uint32_t sp, offset;
unsigned32 mask; uint32_t mask;
PC = cia; PC = cia;
State.regs[REG_SP] += IMM8; State.regs[REG_SP] += IMM8;

33
sim/mn10300/mn10300_sim.h
View File

@ -11,18 +11,11 @@
extern SIM_DESC simulator; extern SIM_DESC simulator;
typedef unsigned8 uint8;
typedef signed8 int8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef struct typedef struct
{ {
uint32 low, high; uint32_t low, high;
} dword; } dword;
typedef uint32 reg_t; typedef uint32_t reg_t;
struct simops struct simops
{ {
@ -160,12 +153,12 @@ u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
PC, read_map, (ADDR))) PC, read_map, (ADDR)))
static INLINE2 dword static INLINE2 dword
u642dw (unsigned64 dw) u642dw (uint64_t dw)
{ {
dword r; dword r;
r.low = (unsigned32)dw; r.low = (uint32_t)dw;
r.high = (unsigned32)(dw >> 32); r.high = (uint32_t)(dw >> 32);
return r; return r;
} }
@ -186,20 +179,20 @@ sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \ sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
PC, write_map, (ADDR), dw2u64 (DATA)) PC, write_map, (ADDR), dw2u64 (DATA))
static INLINE2 unsigned64 static INLINE2 uint64_t
dw2u64 (dword data) dw2u64 (dword data)
{ {
return data.low | (((unsigned64)data.high) << 32); return data.low | (((uint64_t)data.high) << 32);
} }
/* Function declarations. */ /* Function declarations. */
INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg); INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg); INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd); INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg); INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg); INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd); INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd); INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig); void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);

20
sim/mn10300/op_utils.c
View File

@ -25,10 +25,10 @@
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericAdd(unsigned32 source, unsigned32 destReg) genericAdd(uint32_t source, uint32_t destReg)
{ {
int z, c, n, v; int z, c, n, v;
unsigned32 dest, sum; uint32_t dest, sum;
dest = State.regs[destReg]; dest = State.regs[destReg];
sum = source + dest; sum = source + dest;
@ -49,10 +49,10 @@ genericAdd(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericSub(unsigned32 source, unsigned32 destReg) genericSub(uint32_t source, uint32_t destReg)
{ {
int z, c, n, v; int z, c, n, v;
unsigned32 dest, difference; uint32_t dest, difference;
dest = State.regs[destReg]; dest = State.regs[destReg];
difference = dest - source; difference = dest - source;
@ -70,10 +70,10 @@ genericSub(unsigned32 source, unsigned32 destReg)
} }
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) genericCmp(uint32_t leftOpnd, uint32_t rightOpnd)
{ {
int z, c, n, v; int z, c, n, v;
unsigned32 value; uint32_t value;
value = rightOpnd - leftOpnd; value = rightOpnd - leftOpnd;
@ -90,7 +90,7 @@ genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericOr(unsigned32 source, unsigned32 destReg) genericOr(uint32_t source, uint32_t destReg)
{ {
int n, z; int n, z;
@ -103,7 +103,7 @@ genericOr(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericXor(unsigned32 source, unsigned32 destReg) genericXor(uint32_t source, uint32_t destReg)
{ {
int n, z; int n, z;
@ -116,9 +116,9 @@ genericXor(unsigned32 source, unsigned32 destReg)
INLINE_SIM_MAIN (void) INLINE_SIM_MAIN (void)
genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) genericBtst(uint32_t leftOpnd, uint32_t rightOpnd)
{ {
unsigned32 temp; uint32_t temp;
int z, n; int z, n;
temp = rightOpnd; temp = rightOpnd;