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Add support for ARM v6 instructions.

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* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
	* armdefs.h (ARMdval, ARMfval): New types.
	(ARM_VFP_reg): New union.
	(struct ARMul_State): Add VFP_Reg and FPSCR fields.
	(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
	macros for the new VFP_Reg field.
	* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
	QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
	USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
	instructions.
	(handle_VFP_move): New function.
	(ARMul_Emulate16): Add checks for newly supported v6
	instructions.  Add support for VMRS, VMOV and MRC instructions.
	(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
	operating in v6 mode.
	* armemu.h (t_resolved): Define.
	* armsupp.c: Include math.h.
	(handle_VFP_xfer): New function.  Handles VMOV, VSTM, VSTR, VPUSH,
	VSTM, VLDM and VPOP instructions.
	(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
	new handle_VFP_xfer function.
	(ARMul_STC): Likewise.
	(handle_VFP_op): New function.  Handles VMLA, VMLS, VNMLA, VNMLS,
	VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
	VCMPE and VCVT instructions.
	(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
	new handle_VFP_op function.
	* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
	(test_cond): New function.  Tests a condition and returns non-zero
	if the condition has been met.
	(handle_IT_block): New function.
	(in_IT_block): New function.
	(IT_block_allow): New function.
	(ThumbExpandImm): New function.
	(handle_T2_insn): New function.  Handles T2 thumb instructions.
	(handle_v6_thumb_insn): Add next_instr and pc parameters.
	(ARMul_ThumbDecode): Add support for IT blocks.  Add support for
	v6 instructions.
	* wrapper.c (sim_create_inferior): Detect a thumb address and call
	SETT appropriately.
This commit is contained in:
Nick Clifton
2015-06-28 19:14:36 +01:00
parent ee0c0c503d
commit 73cb0348b2
9 changed files with 3882 additions and 127 deletions
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22
sim/arm/armdefs.h
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@ -49,6 +49,25 @@ typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
ARMword value);
typedef double ARMdval; /* FIXME: Must be a 64-bit floating point type. */
typedef float ARMfval; /* FIXME: Must be a 32-bit floating point type. */
typedef union
{
ARMword uword[2];
ARMsword sword[2];
ARMfval fval[2];
ARMdword dword;
ARMdval dval;
} ARM_VFP_reg;
#define VFP_fval(N) (state->VFP_Reg[(N)>> 1].fval[(N) & 1])
#define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1])
#define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1])
#define VFP_dval(N) (state->VFP_Reg[(N)].dval)
#define VFP_dword(N) (state->VFP_Reg[(N)].dword)
struct ARMul_State
{
ARMword Emulate; /* to start and stop emulation */
@ -138,6 +157,9 @@ struct ARMul_State
unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
unsigned verbose; /* Print various messages like the banner */
ARM_VFP_reg VFP_Reg[32]; /* Advanced SIMD registers. */
ARMword FPSCR; /* Floating Point Status Register. */
};
#define ResetPin NresetSig