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FreeBSD x86: Use tramp-frame for signal frames.
Use a register map to describe the registers in mcontext_t as part of the signal frame as is done on several other FreeBSD arches. This permits fetching the fsbase and gsbase register values from the signal frame for both amd64 and i386 and permits fetching additional segment registers stored as 16-bit values on amd64. While signal frames on FreeBSD do contain floating point/XSAVE state, these unwinders do not attempt to supply those registers. The existing x86 signal frame uwinders do not support these registers, and the only existing functions which handle FSAVE/FXSAVE/XSAVE state all work with regcaches. In the future these unwinders could create a tempory regcache, collect floating point registers, and then supply values out of the regcache into the trad-frame.
This commit is contained in:
John Baldwin
@ -18,12 +18,11 @@
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "arch-utils.h"
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#include "frame.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "osabi.h"
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#include "regset.h"
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#include "target.h"
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#include "trad-frame.h"
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#include "tramp-frame.h"
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#include "i386-fbsd-tdep.h"
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#include "gdbsupport/x86-xstate.h"
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@ -70,6 +69,49 @@ static const struct regcache_map_entry amd64_fbsd_gregmap[] =
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{ 0 }
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};
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/* This layout including fsbase and gsbase was adopted in FreeBSD
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8.0. */
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static const struct regcache_map_entry amd64_fbsd_mcregmap[] =
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{
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_onstack */
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{ 1, AMD64_RDI_REGNUM, 0 },
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{ 1, AMD64_RSI_REGNUM, 0 },
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{ 1, AMD64_RDX_REGNUM, 0 },
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{ 1, AMD64_RCX_REGNUM, 0 },
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{ 1, AMD64_R8_REGNUM, 0 },
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{ 1, AMD64_R9_REGNUM, 0 },
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{ 1, AMD64_RAX_REGNUM, 0 },
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{ 1, AMD64_RBX_REGNUM, 0 },
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{ 1, AMD64_RBP_REGNUM, 0 },
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{ 1, AMD64_R10_REGNUM, 0 },
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{ 1, AMD64_R11_REGNUM, 0 },
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{ 1, AMD64_R12_REGNUM, 0 },
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{ 1, AMD64_R13_REGNUM, 0 },
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{ 1, AMD64_R14_REGNUM, 0 },
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{ 1, AMD64_R15_REGNUM, 0 },
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{ 1, REGCACHE_MAP_SKIP, 4 }, /* mc_trapno */
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{ 1, AMD64_FS_REGNUM, 2 },
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{ 1, AMD64_GS_REGNUM, 2 },
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_addr */
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{ 1, REGCACHE_MAP_SKIP, 4 }, /* mc_flags */
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{ 1, AMD64_ES_REGNUM, 2 },
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{ 1, AMD64_DS_REGNUM, 2 },
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_err */
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{ 1, AMD64_RIP_REGNUM, 0 },
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{ 1, AMD64_CS_REGNUM, 8 },
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{ 1, AMD64_EFLAGS_REGNUM, 8 },
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{ 1, AMD64_RSP_REGNUM, 0 },
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{ 1, AMD64_SS_REGNUM, 8 },
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_len */
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_fpformat */
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{ 1, REGCACHE_MAP_SKIP, 8 }, /* mc_ownedfp */
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{ 64, REGCACHE_MAP_SKIP, 8 }, /* mc_fpstate */
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{ 1, AMD64_FSBASE_REGNUM, 0 },
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{ 1, AMD64_GSBASE_REGNUM, 0 },
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{ 0 }
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};
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/* Register set definitions. */
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const struct regset amd64_fbsd_gregset =
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@ -79,80 +121,86 @@ const struct regset amd64_fbsd_gregset =
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/* Support for signal handlers. */
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/* Return whether THIS_FRAME corresponds to a FreeBSD sigtramp
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routine. */
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/* In a signal frame, rsp points to a 'struct sigframe' which is
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defined as:
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static const gdb_byte amd64fbsd_sigtramp_code[] =
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{
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0x48, 0x8d, 0x7c, 0x24, 0x10, /* lea SIGF_UC(%rsp),%rdi */
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0x6a, 0x00, /* pushq $0 */
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0x48, 0xc7, 0xc0, 0xa1, 0x01, 0x00, 0x00,
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/* movq $SYS_sigreturn,%rax */
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0x0f, 0x05 /* syscall */
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};
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struct sigframe {
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union {
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__siginfohandler_t *sf_action;
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__sighandler_t *sf_handler;
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} sf_ahu;
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ucontext_t sf_uc;
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...
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}
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static int
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amd64fbsd_sigtramp_p (struct frame_info *this_frame)
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{
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CORE_ADDR pc = get_frame_pc (this_frame);
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gdb_byte buf[sizeof amd64fbsd_sigtramp_code];
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ucontext_t is defined as:
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if (!safe_frame_unwind_memory (this_frame, pc, buf))
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return 0;
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if (memcmp (buf, amd64fbsd_sigtramp_code, sizeof amd64fbsd_sigtramp_code)
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!= 0)
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return 0;
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struct __ucontext {
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sigset_t uc_sigmask;
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mcontext_t uc_mcontext;
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...
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};
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return 1;
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}
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The mcontext_t contains the general purpose register set as well
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as the floating point or XSAVE state. */
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/* Assuming THIS_FRAME is for a BSD sigtramp routine, return the
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address of the associated sigcontext structure. */
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/* NB: There is an 8 byte padding hole between sf_ahu and sf_uc. */
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#define AMD64_SIGFRAME_UCONTEXT_OFFSET 16
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#define AMD64_UCONTEXT_MCONTEXT_OFFSET 16
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#define AMD64_SIZEOF_MCONTEXT_T 800
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static CORE_ADDR
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amd64fbsd_sigcontext_addr (struct frame_info *this_frame)
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/* Implement the "init" method of struct tramp_frame. */
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static void
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amd64_fbsd_sigframe_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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CORE_ADDR sp;
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gdb_byte buf[8];
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CORE_ADDR sp = get_frame_register_unsigned (this_frame, AMD64_RSP_REGNUM);
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CORE_ADDR mcontext_addr
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= (sp
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+ AMD64_SIGFRAME_UCONTEXT_OFFSET
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+ AMD64_UCONTEXT_MCONTEXT_OFFSET);
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/* The `struct sigcontext' (which really is an `ucontext_t' on
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FreeBSD/amd64) lives at a fixed offset in the signal frame. See
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<machine/sigframe.h>. */
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get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
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sp = extract_unsigned_integer (buf, 8, byte_order);
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return sp + 16;
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trad_frame_set_reg_regmap (this_cache, amd64_fbsd_mcregmap, mcontext_addr,
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AMD64_SIZEOF_MCONTEXT_T);
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/* Don't bother with floating point or XSAVE state for now. The
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current helper routines for parsing FXSAVE and XSAVE state only
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work with regcaches. This could perhaps create a temporary
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regcache, collect the register values from mc_fpstate and
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mc_xfpustate, and then set register values in the trad_frame. */
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trad_frame_set_id (this_cache, frame_id_build (sp, func));
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}
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/* From <machine/signal.h>. */
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int amd64fbsd_sc_reg_offset[] =
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static const struct tramp_frame amd64_fbsd_sigframe =
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{
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24 + 6 * 8, /* %rax */
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24 + 7 * 8, /* %rbx */
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24 + 3 * 8, /* %rcx */
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24 + 2 * 8, /* %rdx */
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24 + 1 * 8, /* %rsi */
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24 + 0 * 8, /* %rdi */
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24 + 8 * 8, /* %rbp */
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24 + 22 * 8, /* %rsp */
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24 + 4 * 8, /* %r8 ... */
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24 + 5 * 8,
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24 + 9 * 8,
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24 + 10 * 8,
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24 + 11 * 8,
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24 + 12 * 8,
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24 + 13 * 8,
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24 + 14 * 8, /* ... %r15 */
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24 + 19 * 8, /* %rip */
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24 + 21 * 8, /* %eflags */
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24 + 20 * 8, /* %cs */
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24 + 23 * 8, /* %ss */
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-1, /* %ds */
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-1, /* %es */
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-1, /* %fs */
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-1 /* %gs */
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SIGTRAMP_FRAME,
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1,
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{
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{0x48, ULONGEST_MAX}, /* lea SIGF_UC(%rsp),%rdi */
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{0x8d, ULONGEST_MAX},
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{0x7c, ULONGEST_MAX},
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{0x24, ULONGEST_MAX},
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{0x10, ULONGEST_MAX},
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{0x6a, ULONGEST_MAX}, /* pushq $0 */
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{0x00, ULONGEST_MAX},
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{0x48, ULONGEST_MAX}, /* movq $SYS_sigreturn,%rax */
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{0xc7, ULONGEST_MAX},
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{0xc0, ULONGEST_MAX},
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{0xa1, ULONGEST_MAX},
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{0x01, ULONGEST_MAX},
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{0x00, ULONGEST_MAX},
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{0x00, ULONGEST_MAX},
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{0x0f, ULONGEST_MAX}, /* syscall */
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{0x05, ULONGEST_MAX},
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{TRAMP_SENTINEL_INSN, ULONGEST_MAX}
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},
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amd64_fbsd_sigframe_init
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};
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/* Implement the core_read_description gdbarch method. */
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@ -245,10 +293,7 @@ amd64fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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amd64_init_abi (info, gdbarch,
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amd64_target_description (X86_XSTATE_SSE_MASK, true));
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tdep->sigtramp_p = amd64fbsd_sigtramp_p;
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tdep->sigcontext_addr = amd64fbsd_sigcontext_addr;
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tdep->sc_reg_offset = amd64fbsd_sc_reg_offset;
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tdep->sc_num_regs = ARRAY_SIZE (amd64fbsd_sc_reg_offset);
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tramp_frame_prepend_unwinder (gdbarch, &amd64_fbsd_sigframe);
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tdep->xsave_xcr0_offset = I386_FBSD_XSAVE_XCR0_OFFSET;
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