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x86: fold AVX vcvtpd2ps memory forms
This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.
This commit is contained in:
Jan Beulich
@ -1,3 +1,8 @@
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2018-03-08 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (operand_type_and_not): New.
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(build_modrm_byte): Use it to prevent clearing unrelated bits.
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2018-03-08 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (ppc_handle_align): Correct last patch. Really
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@ -1785,6 +1785,26 @@ operand_type_and (i386_operand_type x, i386_operand_type y)
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return x;
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}
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static INLINE i386_operand_type
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operand_type_and_not (i386_operand_type x, i386_operand_type y)
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{
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switch (ARRAY_SIZE (x.array))
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{
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case 3:
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x.array [2] &= ~y.array [2];
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/* Fall through. */
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case 2:
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x.array [1] &= ~y.array [1];
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/* Fall through. */
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case 1:
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x.array [0] &= ~y.array [0];
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break;
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default:
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abort ();
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}
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return x;
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}
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static INLINE i386_operand_type
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operand_type_or (i386_operand_type x, i386_operand_type y)
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{
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@ -6867,6 +6887,8 @@ build_modrm_byte (void)
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fake_zero_displacement = 1;
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if (i.index_reg == 0)
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{
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i386_operand_type newdisp;
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gas_assert (!i.tm.opcode_modifier.vecsib);
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/* Operand is just <disp> */
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if (flag_code == CODE_64BIT)
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@ -6878,20 +6900,21 @@ build_modrm_byte (void)
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.sib.base = NO_BASE_REGISTER;
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i.sib.index = NO_INDEX_REGISTER;
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i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
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? disp32s : disp32);
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newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
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}
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else if ((flag_code == CODE_16BIT)
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^ (i.prefix[ADDR_PREFIX] != 0))
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{
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i.rm.regmem = NO_BASE_REGISTER_16;
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i.types[op] = disp16;
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newdisp = disp16;
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}
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else
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{
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i.rm.regmem = NO_BASE_REGISTER;
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i.types[op] = disp32;
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newdisp = disp32;
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}
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i.types[op] = operand_type_and_not (i.types[op], anydisp);
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i.types[op] = operand_type_or (i.types[op], newdisp);
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}
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else if (!i.tm.opcode_modifier.vecsib)
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{
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@ -6973,14 +6996,18 @@ build_modrm_byte (void)
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if (flag_code == CODE_64BIT
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&& operand_type_check (i.types[op], disp))
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{
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i386_operand_type temp;
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operand_type_set (&temp, 0);
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temp.bitfield.disp8 = i.types[op].bitfield.disp8;
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i.types[op] = temp;
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i.types[op].bitfield.disp16 = 0;
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i.types[op].bitfield.disp64 = 0;
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if (i.prefix[ADDR_PREFIX] == 0)
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i.types[op].bitfield.disp32s = 1;
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{
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i.types[op].bitfield.disp32 = 0;
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i.types[op].bitfield.disp32s = 1;
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}
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else
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i.types[op].bitfield.disp32 = 1;
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{
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i.types[op].bitfield.disp32 = 1;
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i.types[op].bitfield.disp32s = 0;
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}
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}
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if (!i.tm.opcode_modifier.vecsib)
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@ -1,3 +1,9 @@
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2018-03-08 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
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forms.
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* i386-tlb.h: Re-generate.
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2018-03-07 Alan Modra <amodra@gmail.com>
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* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
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@ -1997,8 +1997,7 @@ vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_w
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vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
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vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
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vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM }
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vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex, RegXMM }
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vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex, RegXMM }
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vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|Ymmword|BaseIndex, RegXMM }
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vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
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vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
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vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
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@ -37567,24 +37567,7 @@ const insn_template i386_optab[] =
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0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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0, 0, 0 } },
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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0, 0, 0 } } } },
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{ "vcvtpd2ps", 2, 0x665a, None, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
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0, 0, 0 } },
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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