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x86: fold AVX vcvtpd2ps memory forms

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This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
This commit is contained in:
Jan Beulich
2018-03-08 08:25:31 +01:00
committed by Jan Beulich
parent 6a7524c6aa
commit 73053c1fc4
5 changed files with 50 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2018-03-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_and_not): New.
(build_modrm_byte): Use it to prevent clearing unrelated bits.
2018-03-08 Alan Modra <amodra@gmail.com> 2018-03-08 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_handle_align): Correct last patch. Really * config/tc-ppc.c (ppc_handle_align): Correct last patch. Really

43
gas/config/tc-i386.c
View File

@ -1785,6 +1785,26 @@ operand_type_and (i386_operand_type x, i386_operand_type y)
return x; return x;
} }
static INLINE i386_operand_type
operand_type_and_not (i386_operand_type x, i386_operand_type y)
{
switch (ARRAY_SIZE (x.array))
{
case 3:
x.array [2] &= ~y.array [2];
/* Fall through. */
case 2:
x.array [1] &= ~y.array [1];
/* Fall through. */
case 1:
x.array [0] &= ~y.array [0];
break;
default:
abort ();
}
return x;
}
static INLINE i386_operand_type static INLINE i386_operand_type
operand_type_or (i386_operand_type x, i386_operand_type y) operand_type_or (i386_operand_type x, i386_operand_type y)
{ {
@ -6867,6 +6887,8 @@ build_modrm_byte (void)
fake_zero_displacement = 1; fake_zero_displacement = 1;
if (i.index_reg == 0) if (i.index_reg == 0)
{ {
i386_operand_type newdisp;
gas_assert (!i.tm.opcode_modifier.vecsib); gas_assert (!i.tm.opcode_modifier.vecsib);
/* Operand is just <disp> */ /* Operand is just <disp> */
if (flag_code == CODE_64BIT) if (flag_code == CODE_64BIT)
@ -6878,20 +6900,21 @@ build_modrm_byte (void)
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.sib.base = NO_BASE_REGISTER; i.sib.base = NO_BASE_REGISTER;
i.sib.index = NO_INDEX_REGISTER; i.sib.index = NO_INDEX_REGISTER;
i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
? disp32s : disp32);
} }
else if ((flag_code == CODE_16BIT) else if ((flag_code == CODE_16BIT)
^ (i.prefix[ADDR_PREFIX] != 0)) ^ (i.prefix[ADDR_PREFIX] != 0))
{ {
i.rm.regmem = NO_BASE_REGISTER_16; i.rm.regmem = NO_BASE_REGISTER_16;
i.types[op] = disp16; newdisp = disp16;
} }
else else
{ {
i.rm.regmem = NO_BASE_REGISTER; i.rm.regmem = NO_BASE_REGISTER;
i.types[op] = disp32; newdisp = disp32;
} }
i.types[op] = operand_type_and_not (i.types[op], anydisp);
i.types[op] = operand_type_or (i.types[op], newdisp);
} }
else if (!i.tm.opcode_modifier.vecsib) else if (!i.tm.opcode_modifier.vecsib)
{ {
@ -6973,14 +6996,18 @@ build_modrm_byte (void)
if (flag_code == CODE_64BIT if (flag_code == CODE_64BIT
&& operand_type_check (i.types[op], disp)) && operand_type_check (i.types[op], disp))
{ {
i386_operand_type temp; i.types[op].bitfield.disp16 = 0;
operand_type_set (&temp, 0); i.types[op].bitfield.disp64 = 0;
temp.bitfield.disp8 = i.types[op].bitfield.disp8;
i.types[op] = temp;
if (i.prefix[ADDR_PREFIX] == 0) if (i.prefix[ADDR_PREFIX] == 0)
{
i.types[op].bitfield.disp32 = 0;
i.types[op].bitfield.disp32s = 1; i.types[op].bitfield.disp32s = 1;
}
else else
{
i.types[op].bitfield.disp32 = 1; i.types[op].bitfield.disp32 = 1;
i.types[op].bitfield.disp32s = 0;
}
} }
if (!i.tm.opcode_modifier.vecsib) if (!i.tm.opcode_modifier.vecsib)

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2018-03-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
forms.
* i386-tlb.h: Re-generate.
2018-03-07 Alan Modra <amodra@gmail.com> 2018-03-07 Alan Modra <amodra@gmail.com>
* disassemble.c (disassembler): Use bfd_arch_powerpc entry for * disassemble.c (disassembler): Use bfd_arch_powerpc entry for

3
opcodes/i386-opc.tbl
View File

@ -1997,8 +1997,7 @@ vcvtpd2dq, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_w
vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM } vcvtpd2dqx, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM } vcvtpd2dqy, 2, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM } vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM }
vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|BaseIndex, RegXMM } vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Xmmword|Ymmword|BaseIndex, RegXMM }
vcvtpd2ps, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Ymmword|BaseIndex, RegXMM }
vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM } vcvtpd2psx, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM } vcvtpd2psy, 2, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vcvtps2dq, 2, 0x665b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }

19
opcodes/i386-tbl.h
View File

@ -37567,24 +37567,7 @@ const insn_template i386_optab[] =
0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 0 }, 0, 0, 0, 1, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
0, 0, 0 } },
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
0, 0, 0 } } } },
{ "vcvtpd2ps", 2, 0x665a, None, 1,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0 } }, 0, 0, 0 } },
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,