espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-28 07:08:01 +08:00
Code Issues Packages Projects Releases Wiki Activity

[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension

Browse Source 
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
	TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
	RGSR_EL1 and GCR_EL1.
	(aarch64_sys_reg_supported_p): New check for above.
	(aarch64_pstatefields): New entry for TCO.
	(aarch64_pstatefield_supported_p): New check for above.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
	TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
	GCR_EL1 MSR and MRS.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This commit is contained in:
Sudakshina Das
2018-11-12 13:26:01 +00:00
parent 503ba60025
commit 70f3d23af7
6 changed files with 110 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.

26
opcodes/aarch64-opc.c
View File

@ -3929,6 +3929,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
{ "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
{ "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
{ "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
{ "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
{ "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
{ "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
{ "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
{ "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
{ "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
{ "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
@ -4392,6 +4400,18 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
return FALSE;
/* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
if ((reg->value == CPENC (3, 3, C4, C2, 7)
|| reg->value == CPENC (3, 0, C6, C6, 1)
|| reg->value == CPENC (3, 0, C6, C5, 0)
|| reg->value == CPENC (3, 4, C6, C5, 0)
|| reg->value == CPENC (3, 6, C6, C6, 0)
|| reg->value == CPENC (3, 5, C6, C6, 0)
|| reg->value == CPENC (3, 0, C1, C0, 5)
|| reg->value == CPENC (3, 0, C1, C0, 6))
&& !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
return FALSE;
return TRUE;
}
@ -4411,6 +4431,7 @@ const aarch64_sys_reg aarch64_pstatefields [] =
{ "uao", 0x03, F_ARCHEXT },
{ "ssbs", 0x19, F_ARCHEXT },
{ "dit", 0x1a, F_ARCHEXT },
{ "tco", 0x1c, F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@ -4441,6 +4462,11 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
return FALSE;
/* TCO. Values are from aarch64_pstatefields. */
if (reg->value == 0x1c
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
return FALSE;
return TRUE;
}