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Fix verilog output when the width is > 1.

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PR 25202
bfd	* bfd.c (VerilogDataEndianness): New variable.
	(verilog_write_record): Use VerilogDataEndianness, if set, to
	choose the endianness of the output.
	(verilog_write_section): Adjust the address by the data width.

binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
	endianness of the input file.
	(copy_main): Verifiy the value set by the --verilog-data-width
	option.
	* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
	* testsuite/binutils-all/verilog-I4.hex: New file.
This commit is contained in:
Nick Clifton
2022-12-01 13:09:26 +00:00
parent 7505bb034c
commit 6ef35c04df
6 changed files with 102 additions and 8 deletions
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6
binutils/testsuite/binutils-all/verilog-I4.hex Normal file
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@ -0,0 +1,6 @@
@00000000
(01020304|04030201) 00000000.*
@000000..
(02000000|00000002).*
#pass