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[ARC] Provide an interface to decode ARC instructions.
gas/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_opcode_flags): Ignore implicit flags. include/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0, BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes. (flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT flag classes. opcode/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (arc_disassemble_info): New structure. (init_arc_disasm_info): New function. (find_format_from_table): Ignore implicit flags. (find_format): Update dissassembler private data. (print_flags): Likewise. (print_insn_arc): Likewise. (arc_opcode_to_insn_type): Consider the new added instruction classes. (arcAnalyzeInstr): Remove. (arc_insn_decode): New function. * arc-dis.h (arc_ldst_writeback_mode): New enum. (arc_ldst_data_size): Likewise. (arc_condition_code): Likewise. (arc_operand_kind): Likewise. (arc_insn_kind): New struct. (arc_instruction): Likewise. (arc_insn_decode): Declare function. (ARC_Debugger_OperandType): Deleted. (Flow): Likewise. (NullifyMode): Likewise. (allOperandsSize): Likewise. (arcDisState): Likewise. (arcAnalyzeInstr): Likewise. * arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced insn_class_t enums. * arc-opc.c (F_SIZED): New define. (C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise. (C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise. (C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise. (arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags. * opcodes/arc-tbl.h: Update instructions to include new F_CLASS_IMPLICIT flags. (bbit0, lp): Change class. (bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
This commit is contained in:
Claudiu Zissulescu
@ -51,6 +51,33 @@ struct arc_operand_iterator
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const unsigned char *opidx;
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};
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/* A private data used by ARC decoder. */
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struct arc_disassemble_info
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{
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/* The current disassembled arc opcode. */
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const struct arc_opcode *opcode;
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/* Instruction length w/o limm field. */
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unsigned insn_len;
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/* TRUE if we have limm. */
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bfd_boolean limm_p;
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/* LIMM value, if exists. */
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unsigned limm;
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/* Condition code, if exists. */
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unsigned condition_code;
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/* Writeback mode. */
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unsigned writeback_mode;
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/* Number of operands. */
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unsigned operands_count;
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struct arc_insn_operand operands[MAX_INSN_ARGS];
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};
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/* Globals variables. */
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static const char * const regnames[64] =
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@ -108,6 +135,20 @@ static linkclass decodelist = NULL;
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/* Functions implementation. */
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/* Initialize private data. */
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static bfd_boolean
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init_arc_disasm_info (struct disassemble_info *info)
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{
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struct arc_disassemble_info *arc_infop
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= calloc (sizeof (*arc_infop), 1);
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if (arc_infop == NULL)
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return FALSE;
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info->private_data = arc_infop;
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return TRUE;
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}
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/* Add a new element to the decode list. */
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static void
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@ -280,6 +321,10 @@ find_format_from_table (struct disassemble_info *info,
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continue;
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}
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/* Check for the implicit flags. */
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if (cl_flags->flag_class & F_CLASS_IMPLICIT)
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continue;
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand =
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@ -367,6 +412,7 @@ find_format (bfd_vma memaddr,
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bfd_boolean needs_limm;
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const extInstruction_t *einsn, *i;
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unsigned limm = 0;
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struct arc_disassemble_info *arc_infop = info->private_data;
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/* First, try the extension instructions. */
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if (*insn_len == 4)
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@ -422,6 +468,12 @@ An error occured while generating the extension instruction operations");
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}
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*opcode_result = opcode;
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/* Update private data. */
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arc_infop->opcode = opcode;
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arc_infop->limm = (needs_limm) ? limm : 0;
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arc_infop->limm_p = needs_limm;
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return TRUE;
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}
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@ -432,6 +484,7 @@ print_flags (const struct arc_opcode *opcode,
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{
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const unsigned char *flgidx;
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unsigned int value;
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struct arc_disassemble_info *arc_infop = info->private_data;
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/* Now extract and print the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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@ -459,6 +512,18 @@ print_flags (const struct arc_opcode *opcode,
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const struct arc_flag_operand *flg_operand =
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&arc_flag_operands[*flgopridx];
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/* Implicit flags are only used for the insn decoder. */
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if (cl_flags->flag_class & F_CLASS_IMPLICIT)
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{
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if (cl_flags->flag_class & F_CLASS_COND)
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arc_infop->condition_code = flg_operand->code;
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else if (cl_flags->flag_class & F_CLASS_WB)
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arc_infop->writeback_mode = flg_operand->code;
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else if (cl_flags->flag_class & F_CLASS_ZZ)
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info->data_size = flg_operand->code;
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continue;
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}
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if (!flg_operand->favail)
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continue;
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@ -496,8 +561,13 @@ print_flags (const struct arc_opcode *opcode,
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info->insn_type = dis_condjsr;
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else if (info->insn_type == dis_branch)
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info->insn_type = dis_condbranch;
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arc_infop->condition_code = flg_operand->code;
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}
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/* Check for the write back modes. */
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if (cl_flags->flag_class & F_CLASS_WB)
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arc_infop->writeback_mode = flg_operand->code;
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(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
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}
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}
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@ -733,7 +803,15 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
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switch (opcode->insn_class)
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{
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case BRANCH:
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case BBIT0:
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case BBIT1:
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case BI:
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case BIH:
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case BRCC:
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case EI:
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case JLI:
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case JUMP:
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case LOOP:
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if (!strncmp (opcode->name, "bl", 2)
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|| !strncmp (opcode->name, "jl", 2))
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{
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@ -753,8 +831,14 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
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case LOAD:
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case STORE:
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case MEMORY:
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case ENTER:
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case PUSH:
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case POP:
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insn_type = dis_dref;
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break;
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case LEAVE:
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insn_type = dis_branch;
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break;
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default:
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insn_type = dis_nonbranch;
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break;
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@ -783,6 +867,7 @@ print_insn_arc (bfd_vma memaddr,
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int value;
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struct arc_operand_iterator iter;
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Elf_Internal_Ehdr *header = NULL;
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struct arc_disassemble_info *arc_infop;
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if (info->disassembler_options)
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{
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@ -792,6 +877,9 @@ print_insn_arc (bfd_vma memaddr,
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info->disassembler_options = NULL;
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}
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if (info->private_data == NULL && !init_arc_disasm_info (info))
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return -1;
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memset (&iter, 0, sizeof (iter));
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highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
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lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
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@ -813,7 +901,7 @@ print_insn_arc (bfd_vma memaddr,
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default:
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isa_mask = ARC_OPCODE_ARCv2EM;
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/* TODO: Perhaps remove defitinion of header since it is only used at
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this location. */
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this location. */
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if (header != NULL
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&& (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
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{
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@ -899,6 +987,8 @@ print_insn_arc (bfd_vma memaddr,
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insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info);
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pr_debug ("instruction length = %d bytes\n", insn_len);
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arc_infop = info->private_data;
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arc_infop->insn_len = insn_len;
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switch (insn_len)
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{
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@ -957,7 +1047,7 @@ print_insn_arc (bfd_vma memaddr,
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/* Set some defaults for the insn info. */
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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info->data_size = 0;
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info->data_size = 4;
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info->insn_type = dis_nonbranch;
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info->target = 0;
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info->target2 = 0;
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@ -1016,6 +1106,7 @@ print_insn_arc (bfd_vma memaddr,
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need_comma = FALSE;
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open_braket = FALSE;
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arc_infop->operands_count = 0;
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/* Now extract and print the operands. */
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operand = NULL;
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@ -1034,14 +1125,14 @@ print_insn_arc (bfd_vma memaddr,
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if ((operand->flags & ARC_OPERAND_IGNORE)
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&& (operand->flags & ARC_OPERAND_IR)
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&& value == -1)
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&& value == -1)
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continue;
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if (operand->flags & ARC_OPERAND_COLON)
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{
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(*info->fprintf_func) (info->stream, ":");
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continue;
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}
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{
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(*info->fprintf_func) (info->stream, ":");
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continue;
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}
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if (need_comma)
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(*info->fprintf_func) (info->stream, ",");
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@ -1106,12 +1197,12 @@ print_insn_arc (bfd_vma memaddr,
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(*info->fprintf_func) (info->stream, "%d", value);
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}
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else if (operand->flags & ARC_OPERAND_ADDRTYPE)
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{
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const char *addrtype = get_addrtype (value);
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(*info->fprintf_func) (info->stream, "%s", addrtype);
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/* A colon follow an address type. */
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need_comma = FALSE;
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}
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{
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const char *addrtype = get_addrtype (value);
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(*info->fprintf_func) (info->stream, "%s", addrtype);
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/* A colon follow an address type. */
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need_comma = FALSE;
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}
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else
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{
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if (operand->flags & ARC_OPERAND_TRUNCATE
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@ -1129,6 +1220,24 @@ print_insn_arc (bfd_vma memaddr,
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(*info->fprintf_func) (info->stream, "%#x", value);
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}
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}
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if (operand->flags & ARC_OPERAND_LIMM)
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{
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arc_infop->operands[arc_infop->operands_count].kind
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= ARC_OPERAND_KIND_LIMM;
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/* It is not important to have exactly the LIMM indicator
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here. */
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arc_infop->operands[arc_infop->operands_count].value = 63;
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}
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else
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{
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arc_infop->operands[arc_infop->operands_count].value = value;
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arc_infop->operands[arc_infop->operands_count].kind
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= (operand->flags & ARC_OPERAND_IR
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? ARC_OPERAND_KIND_REG
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: ARC_OPERAND_KIND_SHIMM);
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}
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arc_infop->operands_count ++;
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}
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return insn_len;
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@ -1152,30 +1261,6 @@ arc_get_disassembler (bfd *abfd)
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return print_insn_arc;
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}
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/* Disassemble ARC instructions. Used by debugger. */
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struct arcDisState
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arcAnalyzeInstr (bfd_vma memaddr,
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struct disassemble_info *info)
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{
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struct arcDisState ret;
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memset (&ret, 0, sizeof (struct arcDisState));
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ret.instructionLen = print_insn_arc (memaddr, info);
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#if 0
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ret.words[0] = insn[0];
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ret.words[1] = insn[1];
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ret._this = &ret;
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ret.coreRegName = _coreRegName;
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ret.auxRegName = _auxRegName;
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ret.condCodeName = _condCodeName;
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ret.instName = _instName;
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#endif
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return ret;
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}
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void
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print_arc_disassembler_options (FILE *stream)
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{
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@ -1199,6 +1284,58 @@ with -M switch (multiple options should be separated by commas):\n"));
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fpud Recognize double precision FPU instructions.\n"));
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}
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void arc_insn_decode (bfd_vma addr,
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struct disassemble_info *info,
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disassembler_ftype disasm_func,
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struct arc_instruction *insn)
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{
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const struct arc_opcode *opcode;
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struct arc_disassemble_info *arc_infop;
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/* Ensure that insn would be in the reset state. */
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memset (insn, 0, sizeof (struct arc_instruction));
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/* There was an error when disassembling, for example memory read error. */
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if (disasm_func (addr, info) < 0)
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{
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insn->valid = FALSE;
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return;
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}
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assert (info->private_data != NULL);
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arc_infop = info->private_data;
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insn->length = arc_infop->insn_len;;
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insn->address = addr;
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/* Quick exit if memory at this address is not an instruction. */
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if (info->insn_type == dis_noninsn)
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{
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insn->valid = FALSE;
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return;
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}
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insn->valid = TRUE;
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opcode = (const struct arc_opcode *) arc_infop->opcode;
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insn->insn_class = opcode->insn_class;
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insn->limm_value = arc_infop->limm;
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insn->limm_p = arc_infop->limm_p;
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insn->is_control_flow = (info->insn_type == dis_branch
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|| info->insn_type == dis_condbranch
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|| info->insn_type == dis_jsr
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|| info->insn_type == dis_condjsr);
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insn->has_delay_slot = info->branch_delay_insns;
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insn->writeback_mode
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= (enum arc_ldst_writeback_mode) arc_infop->writeback_mode;
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insn->data_size_mode = info->data_size;
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insn->condition_code = arc_infop->condition_code;
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memcpy (insn->operands, arc_infop->operands,
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sizeof (struct arc_insn_operand) * MAX_INSN_ARGS);
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insn->operands_count = arc_infop->operands_count;
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}
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/* Local variables:
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eval: (c-set-style "gnu")
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