RISC-V: Add T-Head MemPair vendor extension

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/elfxx-riscv.c

@@ -1232,6 +1232,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadfmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -2411,6 +2412,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadmac");
     case INSN_CLASS_XTHEADMEMIDX:
       return riscv_subset_supports (rps, "xtheadmemidx");
+    case INSN_CLASS_XTHEADMEMPAIR:
+      return riscv_subset_supports (rps, "xtheadmempair");
     case INSN_CLASS_XTHEADSYNC:
       return riscv_subset_supports (rps, "xtheadsync");
     default:
@@ -2556,6 +2559,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadmac";
     case INSN_CLASS_XTHEADMEMIDX:
       return "xtheadmemidx";
+    case INSN_CLASS_XTHEADMEMPAIR:
+      return "xtheadmempair";
     case INSN_CLASS_XTHEADSYNC:
       return "xtheadsync";
     default:

gas/doc/c-riscv.texi

@@ -744,6 +744,11 @@ The XTheadMemIdx extension provides GPR memory operations.
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 
+@item XTheadMemPair
+The XTheadMemPair extension provides two-GP-register memory operations.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
 @item XTheadSync
 The XTheadSync extension provides instructions for multi-processor synchronization.
 

gas/testsuite/gas/riscv/x-thead-mempair-fail.d

@@ -0,0 +1,3 @@
+#as: -march=rv64gc_xtheadmempair
+#source: x-thead-mempair-fail.s
+#error_output: x-thead-mempair-fail.l

gas/testsuite/gas/riscv/x-thead-mempair-fail.l

@@ -0,0 +1,30 @@
+.*: Assembler messages:
+.*: Error: illegal operands `th.ldd a0,a1,\(a2\),0'
+.*: Error: illegal operands `th.lwd a0,a1,\(a2\),1'
+.*: Error: illegal operands `th.lwud a0,a1,\(a2\),2'
+.*: Error: illegal operands `th.sdd a0,a1,\(a2\),3'
+.*: Error: illegal operands `th.swd a0,a1,\(a2\),0'
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+.*: Error: unexpected literal \(3\)
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+.*: Error: unexpected literal \(4\)
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+.*: Error: unexpected literal \(4\)
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+.*: Error: unexpected literal \(3\)
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+.*: Error: unexpected literal \(4\)
+
+.*: Error: illegal operands `th.ldd a0,a0,\(a1\),0'
+.*: Error: illegal operands `th.ldd a0,a1,\(a0\),0'
+.*: Error: illegal operands `th.ldd a1,a0,\(a0\),0'

gas/testsuite/gas/riscv/x-thead-mempair-fail.s

@@ -0,0 +1,30 @@
+target:
+	th.ldd		a0, a1, (a2), 0
+	th.lwd		a0, a1, (a2), 1
+	th.lwud		a0, a1, (a2), 2
+	th.sdd		a0, a1, (a2), 3
+	th.swd		a0, a1, (a2), 0
+
+	th.ldd		a0, a1, (a2), -1, 4
+	th.ldd		a0, a1, (a2), 4, 4
+	th.ldd		a0, a1, (a2), 0, 3
+
+	th.lwd		a0, a1, (a2), -1, 3
+	th.lwd		a0, a1, (a2), 4, 3
+	th.lwd		a0, a1, (a2), 0, 4
+
+	th.lwud		a0, a1, (a2), -1, 3
+	th.lwud		a0, a1, (a2), 4, 3
+	th.lwud		a0, a1, (a2), 0, 4
+
+	th.sdd		a0, a1, (a2), -1, 4
+	th.sdd		a0, a1, (a2), 4, 4
+	th.sdd		a0, a1, (a2), 0, 3
+
+	th.swd		a0, a1, (a2), -1, 3
+	th.swd		a0, a1, (a2), 4, 3
+	th.swd		a0, a1, (a2), 0, 4
+
+	th.ldd		a0, a0, (a1), 0
+	th.ldd		a0, a1, (a0), 0
+	th.ldd		a1, a0, (a0), 0

gas/testsuite/gas/riscv/x-thead-mempair.d

@@ -0,0 +1,14 @@
+#as: -march=rv64gc_xtheadmempair
+#source: x-thead-mempair.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+f8b6450b[ 	]+th.ldd[ 	]+a0,a1,\(a2\),0,4
+[ 	]+[0-9a-f]+:[ 	]+e2b6450b[ 	]+th.lwd[ 	]+a0,a1,\(a2\),1,3
+[ 	]+[0-9a-f]+:[ 	]+f4b6450b[ 	]+th.lwud[ 	]+a0,a1,\(a2\),2,3
+[ 	]+[0-9a-f]+:[ 	]+feb6550b[ 	]+th.sdd[ 	]+a0,a1,\(a2\),3,4
+[ 	]+[0-9a-f]+:[ 	]+e0b6550b[ 	]+th.swd[ 	]+a0,a1,\(a2\),0,3

gas/testsuite/gas/riscv/x-thead-mempair.s

@@ -0,0 +1,6 @@
+target:
+	th.ldd		a0, a1, (a2), 0, 4
+	th.lwd		a0, a1, (a2), 1, 3
+	th.lwud		a0, a1, (a2), 2, 3
+	th.sdd		a0, a1, (a2), 3, 4
+	th.swd		a0, a1, (a2), 0, 3

include/opcode/riscv-opc.h

@@ -2216,6 +2216,17 @@
 #define MASK_TH_MULSH 0xfe00707f
 #define MATCH_TH_MULSW 0x2600100b
 #define MASK_TH_MULSW 0xfe00707f
+/* Vendor-specific (T-Head) XTheadMemPair instructions. */
+#define MATCH_TH_LDD 0xf800400b
+#define MASK_TH_LDD 0xf800707f
+#define MATCH_TH_LWD 0xe000400b
+#define MASK_TH_LWD 0xf800707f
+#define MATCH_TH_LWUD 0xf000400b
+#define MASK_TH_LWUD 0xf800707f
+#define MATCH_TH_SDD 0xf800500b
+#define MASK_TH_SDD 0xf800707f
+#define MATCH_TH_SWD 0xe000500b
+#define MASK_TH_SWD 0xf800707f
 /* Vendor-specific (T-Head) XTheadMemIdx instructions. */
 #define MATCH_TH_LDIA 0x7800400b
 #define MASK_TH_LDIA 0xf800707f
@@ -3155,6 +3166,12 @@ DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD)
 DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW)
 DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH)
 DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB)
+/* Vendor-specific (T-Head) XTheadMemPair instructions. */
+DECLARE_INSN(th_ldd, MATCH_TH_LDD, MASK_TH_LDD)
+DECLARE_INSN(th_lwd, MATCH_TH_LWD, MASK_TH_LWD)
+DECLARE_INSN(th_lwud, MATCH_TH_LWUD, MASK_TH_LWUD)
+DECLARE_INSN(th_sdd, MATCH_TH_SDD, MASK_TH_SDD)
+DECLARE_INSN(th_swd, MATCH_TH_SWD, MASK_TH_SWD)
 /* Vendor-specific (T-Head) XTheadSync instructions.  */
 DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
 DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)

include/opcode/riscv.h

@@ -423,6 +423,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADFMEMIDX,
   INSN_CLASS_XTHEADMAC,
   INSN_CLASS_XTHEADMEMIDX,
+  INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
 };
 

opcodes/riscv-opc.c

@@ -278,6 +278,23 @@ match_th_load_inc(const struct riscv_opcode *op,
   return rd != rs1 && match_opcode (op, insn);
 }
 
+static int
+match_th_load_pair(const struct riscv_opcode *op,
+		     insn_t insn)
+{
+  /* Load pair instructions use the following encoding:
+   * - rd1 = RD (insn[11:7])
+   * - rd2 = RS2 (insn[24:20])
+   * - rs = RS1 ([19:15])
+   * This function matches if the following restriction is met:
+   * The values of rd1, rd2, and rs1 must not be the same.  */
+  int rd1 = (insn & MASK_RD) >> OP_SH_RD;
+  int rd2 = (insn & MASK_RS2) >> OP_SH_RS2;
+  int rs = (insn & MASK_RS1) >> OP_SH_RS1;
+
+  return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn);
+}
+
 const struct riscv_opcode riscv_opcodes[] =
 {
 /* name, xlen, isa, operands, match, mask, match_func, pinfo.  */
@@ -1941,6 +1958,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.surh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH,  MASK_TH_SURH, match_opcode, 0},
 {"th.surb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB,  MASK_TH_SURB, match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadMemPair instructions.  */
+{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_LDD,  MASK_TH_LDD,  match_th_load_pair, 0},
+{"th.lwd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWD,  MASK_TH_LWD,  match_th_load_pair, 0},
+{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0},
+{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", MATCH_TH_SDD,  MASK_TH_SDD,  match_opcode, 0},
+{"th.swd",  0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", MATCH_TH_SWD,  MASK_TH_SWD,  match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadMac instructions.  */
 {"th.mula",          0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA,  MASK_TH_MULA,  match_opcode, 0},
 {"th.mulah",         0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0},