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Add support for SPARC T4 crypto instructions.
include/opcode/ * sparc.h: Document new arg code' )' for crypto RS3 immediates. opcodes/ * sparc-dis.c (print_insn_sparc): Handle ')'. * sparc-opc.c (sparc_opcodes): Add crypto instructions. gas/ * config/tc-sparc.c (sparc_ip): Likewise. Accept instruction names containing "_". (sparc_arch_table): Add sparc4, v8pluse, and v9e. Add crypto hwcap masks to v8plusv and v9v. gas/testsuite/ * gas/sparc/crypto.s: New file. * gas/sparc/crypto.d: New file. * gas/sparc/sparc.exp: Run crypto test.
This commit is contained in:
David S. Miller
@ -1,5 +1,10 @@
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2012-04-27 David S. Miller <davem@davemloft.net>
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2012-04-27 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (sparc_ip): Likewise. Accept instruction
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names containing "_".
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(sparc_arch_table): Add sparc4, v8pluse, and v9e. Add crypto
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hwcap masks to v8plusv and v9v.
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* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
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* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
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masks.
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masks.
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(sparc_md_end): No longer need to translate hwcap_seen values into
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(sparc_md_end): No longer need to translate hwcap_seen values into
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@ -245,6 +245,7 @@ static struct sparc_arch {
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{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
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{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
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{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
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{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
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{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
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{ "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
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{ "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
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{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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@ -254,13 +255,15 @@ static struct sparc_arch {
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{ "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
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{ "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
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{ "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
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{ "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
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{ "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
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{ "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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{ "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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{ "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
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{ "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
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{ "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
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{ "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
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{ "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
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{ "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
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{ "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
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/* This exists to allow configure.in/Makefile.in to pass one
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/* This exists to allow configure.in/Makefile.in to pass one
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value to specify both the default machine and default word size. */
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value to specify both the default machine and default word size. */
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{ "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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{ "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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@ -1487,7 +1490,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
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{
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{
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do
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do
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++s;
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++s;
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while (ISLOWER (*s) || ISDIGIT (*s));
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while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
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}
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}
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switch (*s)
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switch (*s)
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@ -1799,6 +1802,47 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
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the_insn.reloc = BFD_RELOC_SPARC_10;
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the_insn.reloc = BFD_RELOC_SPARC_10;
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goto immediate;
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goto immediate;
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case ')':
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if (*s == ' ')
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s++;
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if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
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|| ISDIGIT (*s))
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{
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long num = 0;
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if (s[0] == '0' && s[1] == 'x')
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{
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s += 2;
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while (ISXDIGIT (*s))
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{
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num <<= 4;
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num |= hex_value (*s);
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++s;
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}
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}
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else
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{
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while (ISDIGIT (*s))
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{
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num = num * 10 + *s - '0';
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++s;
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}
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}
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if (num < 0 || num > 31)
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{
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error_message = _(": crypto immediate must be between 0 and 31");
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goto error;
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}
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opcode |= RS3 (num);
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continue;
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}
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else
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{
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error_message = _(": expecting crypto immediate");
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goto error;
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}
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case 'X':
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case 'X':
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/* V8 systems don't understand BFD_RELOC_SPARC_5. */
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/* V8 systems don't understand BFD_RELOC_SPARC_5. */
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if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
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if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
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@ -1,3 +1,9 @@
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2012-04-27 David S. Miller <davem@davemloft.net>
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* gas/sparc/crypto.s: New file.
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* gas/sparc/crypto.d: New file.
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* gas/sparc/sparc.exp: Run crypto test.
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2012-04-12 David S. Miller <davem@davemloft.net>
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2012-04-12 David S. Miller <davem@davemloft.net>
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* gas/sparc/reloc64.s: Add abs34 code model tests.
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* gas/sparc/reloc64.s: Add abs34 code model tests.
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132
gas/testsuite/gas/sparc/crypto.d
Normal file
132
gas/testsuite/gas/sparc/crypto.d
Normal file
@ -0,0 +1,132 @@
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#as: -Av9v
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#objdump: -dr
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#name: sparc CRYPTO
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.*: +file format .*sparc.*
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Disassembly of section .text:
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0+ <.text>:
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0: 81 b0 28 00 md5
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4: 81 b0 28 20 sha1
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8: 81 b0 28 40 sha256
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c: 81 b0 28 60 sha512
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10: 8d b0 a8 e4 crc32c %f2, %f4, %f6
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14: 91 b1 26 06 aes_kexpand0 %f4, %f6, %f8
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18: 94 41 8f 08 aes_kexpand1 %f6, %f8, 0x7, %f10
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1c: 94 41 8d 08 aes_kexpand1 %f6, %f8, 0x6, %f10
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20: 99 b2 26 2a aes_kexpand2 %f8, %f10, %f12
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24: a0 42 9c 0c aes_eround01 %f10, %f12, %f14, %f16
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28: a4 43 20 2e aes_eround23 %f12, %f14, %f16, %f18
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2c: a8 43 a4 50 aes_dround01 %f14, %f16, %f18, %f20
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30: ac 44 28 72 aes_dround23 %f16, %f18, %f20, %f22
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34: b0 44 ac 94 aes_eround01_l %f18, %f20, %f22, %f24
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38: b4 45 30 b6 aes_eround23_l %f20, %f22, %f24, %f26
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3c: b8 45 b4 d8 aes_dround01_l %f22, %f24, %f26, %f28
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40: bc 46 38 fa aes_dround23_l %f24, %f26, %f28, %f30
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44: 87 b0 66 80 des_ip %f32, %f34
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48: 8b b0 e6 a0 des_iip %f34, %f36
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4c: 8f b1 66 c7 des_kexpand %f36, 7, %f38
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50: 9a 41 d7 29 des_round %f38, %f40, %f42, %f44
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54: 9f b2 e7 0d kasumi_fi_fi %f42, %f44, %f46
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58: a6 43 63 4f kasumi_fl_xor %f44, %f46, %f48, %f50
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5c: aa 43 e7 71 kasumi_fi_xor %f46, %f48, %f50, %f52
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60: af b4 e7 95 camellia_fi %f50, %f52, %f54
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64: b3 b5 67 b7 camellia_fli %f52, %f54, %f56
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68: ba 45 f7 99 camellia_f %f54, %f56, %f58, %f60
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6c: 81 b0 29 00 mpmul 0
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70: 81 b0 29 01 mpmul 1
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74: 81 b0 29 02 mpmul 2
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78: 81 b0 29 03 mpmul 3
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7c: 81 b0 29 04 mpmul 4
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80: 81 b0 29 05 mpmul 5
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84: 81 b0 29 06 mpmul 6
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88: 81 b0 29 07 mpmul 7
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8c: 81 b0 29 08 mpmul 8
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90: 81 b0 29 09 mpmul 9
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94: 81 b0 29 0a mpmul 0xa
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|
98: 81 b0 29 0b mpmul 0xb
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9c: 81 b0 29 0c mpmul 0xc
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a0: 81 b0 29 0d mpmul 0xd
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a4: 81 b0 29 0e mpmul 0xe
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a8: 81 b0 29 0f mpmul 0xf
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ac: 81 b0 29 10 mpmul 0x10
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b0: 81 b0 29 11 mpmul 0x11
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b4: 81 b0 29 12 mpmul 0x12
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b8: 81 b0 29 13 mpmul 0x13
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bc: 81 b0 29 14 mpmul 0x14
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c0: 81 b0 29 15 mpmul 0x15
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c4: 81 b0 29 16 mpmul 0x16
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c8: 81 b0 29 17 mpmul 0x17
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cc: 81 b0 29 18 mpmul 0x18
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d0: 81 b0 29 19 mpmul 0x19
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d4: 81 b0 29 1a mpmul 0x1a
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d8: 81 b0 29 1b mpmul 0x1b
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dc: 81 b0 29 1c mpmul 0x1c
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e0: 81 b0 29 1d mpmul 0x1d
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e4: 81 b0 29 1e mpmul 0x1e
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e8: 81 b0 29 1f mpmul 0x1f
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ec: 81 b0 29 20 montmul 0
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f0: 81 b0 29 21 montmul 1
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f4: 81 b0 29 22 montmul 2
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f8: 81 b0 29 23 montmul 3
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|
fc: 81 b0 29 24 montmul 4
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|
100: 81 b0 29 25 montmul 5
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|
104: 81 b0 29 26 montmul 6
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|
108: 81 b0 29 27 montmul 7
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|
10c: 81 b0 29 28 montmul 8
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|
110: 81 b0 29 29 montmul 9
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114: 81 b0 29 2a montmul 0xa
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118: 81 b0 29 2b montmul 0xb
|
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|
11c: 81 b0 29 2c montmul 0xc
|
||||||
|
120: 81 b0 29 2d montmul 0xd
|
||||||
|
124: 81 b0 29 2e montmul 0xe
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||||||
|
128: 81 b0 29 2f montmul 0xf
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||||||
|
12c: 81 b0 29 30 montmul 0x10
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||||||
|
130: 81 b0 29 31 montmul 0x11
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|
134: 81 b0 29 32 montmul 0x12
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||||||
|
138: 81 b0 29 33 montmul 0x13
|
||||||
|
13c: 81 b0 29 34 montmul 0x14
|
||||||
|
140: 81 b0 29 35 montmul 0x15
|
||||||
|
144: 81 b0 29 36 montmul 0x16
|
||||||
|
148: 81 b0 29 37 montmul 0x17
|
||||||
|
14c: 81 b0 29 38 montmul 0x18
|
||||||
|
150: 81 b0 29 39 montmul 0x19
|
||||||
|
154: 81 b0 29 3a montmul 0x1a
|
||||||
|
158: 81 b0 29 3b montmul 0x1b
|
||||||
|
15c: 81 b0 29 3c montmul 0x1c
|
||||||
|
160: 81 b0 29 3d montmul 0x1d
|
||||||
|
164: 81 b0 29 3e montmul 0x1e
|
||||||
|
168: 81 b0 29 3f montmul 0x1f
|
||||||
|
16c: 81 b0 29 40 montsqr 0
|
||||||
|
170: 81 b0 29 41 montsqr 1
|
||||||
|
174: 81 b0 29 42 montsqr 2
|
||||||
|
178: 81 b0 29 43 montsqr 3
|
||||||
|
17c: 81 b0 29 44 montsqr 4
|
||||||
|
180: 81 b0 29 45 montsqr 5
|
||||||
|
184: 81 b0 29 46 montsqr 6
|
||||||
|
188: 81 b0 29 47 montsqr 7
|
||||||
|
18c: 81 b0 29 48 montsqr 8
|
||||||
|
190: 81 b0 29 49 montsqr 9
|
||||||
|
194: 81 b0 29 4a montsqr 0xa
|
||||||
|
198: 81 b0 29 4b montsqr 0xb
|
||||||
|
19c: 81 b0 29 4c montsqr 0xc
|
||||||
|
1a0: 81 b0 29 4d montsqr 0xd
|
||||||
|
1a4: 81 b0 29 4e montsqr 0xe
|
||||||
|
1a8: 81 b0 29 4f montsqr 0xf
|
||||||
|
1ac: 81 b0 29 50 montsqr 0x10
|
||||||
|
1b0: 81 b0 29 51 montsqr 0x11
|
||||||
|
1b4: 81 b0 29 52 montsqr 0x12
|
||||||
|
1b8: 81 b0 29 53 montsqr 0x13
|
||||||
|
1bc: 81 b0 29 54 montsqr 0x14
|
||||||
|
1c0: 81 b0 29 55 montsqr 0x15
|
||||||
|
1c4: 81 b0 29 56 montsqr 0x16
|
||||||
|
1c8: 81 b0 29 57 montsqr 0x17
|
||||||
|
1cc: 81 b0 29 58 montsqr 0x18
|
||||||
|
1d0: 81 b0 29 59 montsqr 0x19
|
||||||
|
1d4: 81 b0 29 5a montsqr 0x1a
|
||||||
|
1d8: 81 b0 29 5b montsqr 0x1b
|
||||||
|
1dc: 81 b0 29 5c montsqr 0x1c
|
||||||
|
1e0: 81 b0 29 5d montsqr 0x1d
|
||||||
|
1e4: 81 b0 29 5e montsqr 0x1e
|
||||||
|
1e8: 81 b0 29 5f montsqr 0x1f
|
||||||
125
gas/testsuite/gas/sparc/crypto.s
Normal file
125
gas/testsuite/gas/sparc/crypto.s
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
# Test CRYPTO instructions
|
||||||
|
.text
|
||||||
|
md5
|
||||||
|
sha1
|
||||||
|
sha256
|
||||||
|
sha512
|
||||||
|
crc32c %f2, %f4, %f6
|
||||||
|
aes_kexpand0 %f4, %f6, %f8
|
||||||
|
aes_kexpand1 %f6, %f8, 0x7, %f10
|
||||||
|
aes_kexpand1 %f6, %f8, 6, %f10
|
||||||
|
aes_kexpand2 %f8, %f10, %f12
|
||||||
|
aes_eround01 %f10, %f12, %f14, %f16
|
||||||
|
aes_eround23 %f12, %f14, %f16, %f18
|
||||||
|
aes_dround01 %f14, %f16, %f18, %f20
|
||||||
|
aes_dround23 %f16, %f18, %f20, %f22
|
||||||
|
aes_eround01_l %f18, %f20, %f22, %f24
|
||||||
|
aes_eround23_l %f20, %f22, %f24, %f26
|
||||||
|
aes_dround01_l %f22, %f24, %f26, %f28
|
||||||
|
aes_dround23_l %f24, %f26, %f28, %f30
|
||||||
|
des_ip %f32, %f34
|
||||||
|
des_iip %f34, %f36
|
||||||
|
des_kexpand %f36, 7, %f38
|
||||||
|
des_round %f38, %f40, %f42, %f44
|
||||||
|
kasumi_fi_fi %f42, %f44, %f46
|
||||||
|
kasumi_fl_xor %f44, %f46, %f48, %f50
|
||||||
|
kasumi_fi_xor %f46, %f48, %f50, %f52
|
||||||
|
camellia_fi %f50, %f52, %f54
|
||||||
|
camellia_fli %f52, %f54, %f56
|
||||||
|
camellia_f %f54, %f56, %f58, %f60
|
||||||
|
mpmul 0
|
||||||
|
mpmul 1
|
||||||
|
mpmul 2
|
||||||
|
mpmul 3
|
||||||
|
mpmul 4
|
||||||
|
mpmul 5
|
||||||
|
mpmul 6
|
||||||
|
mpmul 7
|
||||||
|
mpmul 8
|
||||||
|
mpmul 9
|
||||||
|
mpmul 10
|
||||||
|
mpmul 11
|
||||||
|
mpmul 12
|
||||||
|
mpmul 13
|
||||||
|
mpmul 14
|
||||||
|
mpmul 15
|
||||||
|
mpmul 16
|
||||||
|
mpmul 17
|
||||||
|
mpmul 18
|
||||||
|
mpmul 19
|
||||||
|
mpmul 20
|
||||||
|
mpmul 21
|
||||||
|
mpmul 22
|
||||||
|
mpmul 23
|
||||||
|
mpmul 24
|
||||||
|
mpmul 25
|
||||||
|
mpmul 26
|
||||||
|
mpmul 27
|
||||||
|
mpmul 28
|
||||||
|
mpmul 29
|
||||||
|
mpmul 30
|
||||||
|
mpmul 31
|
||||||
|
montmul 0
|
||||||
|
montmul 1
|
||||||
|
montmul 2
|
||||||
|
montmul 3
|
||||||
|
montmul 4
|
||||||
|
montmul 5
|
||||||
|
montmul 6
|
||||||
|
montmul 7
|
||||||
|
montmul 8
|
||||||
|
montmul 9
|
||||||
|
montmul 10
|
||||||
|
montmul 11
|
||||||
|
montmul 12
|
||||||
|
montmul 13
|
||||||
|
montmul 14
|
||||||
|
montmul 15
|
||||||
|
montmul 16
|
||||||
|
montmul 17
|
||||||
|
montmul 18
|
||||||
|
montmul 19
|
||||||
|
montmul 20
|
||||||
|
montmul 21
|
||||||
|
montmul 22
|
||||||
|
montmul 23
|
||||||
|
montmul 24
|
||||||
|
montmul 25
|
||||||
|
montmul 26
|
||||||
|
montmul 27
|
||||||
|
montmul 28
|
||||||
|
montmul 29
|
||||||
|
montmul 30
|
||||||
|
montmul 31
|
||||||
|
montsqr 0
|
||||||
|
montsqr 1
|
||||||
|
montsqr 2
|
||||||
|
montsqr 3
|
||||||
|
montsqr 4
|
||||||
|
montsqr 5
|
||||||
|
montsqr 6
|
||||||
|
montsqr 7
|
||||||
|
montsqr 8
|
||||||
|
montsqr 9
|
||||||
|
montsqr 10
|
||||||
|
montsqr 11
|
||||||
|
montsqr 12
|
||||||
|
montsqr 13
|
||||||
|
montsqr 14
|
||||||
|
montsqr 15
|
||||||
|
montsqr 16
|
||||||
|
montsqr 17
|
||||||
|
montsqr 18
|
||||||
|
montsqr 19
|
||||||
|
montsqr 20
|
||||||
|
montsqr 21
|
||||||
|
montsqr 22
|
||||||
|
montsqr 23
|
||||||
|
montsqr 24
|
||||||
|
montsqr 25
|
||||||
|
montsqr 26
|
||||||
|
montsqr 27
|
||||||
|
montsqr 28
|
||||||
|
montsqr 29
|
||||||
|
montsqr 30
|
||||||
|
montsqr 31
|
||||||
@ -62,6 +62,7 @@ if [istarget sparc*-*-*] {
|
|||||||
run_dump_test "pc2210"
|
run_dump_test "pc2210"
|
||||||
run_dump_test "hpcvis3"
|
run_dump_test "hpcvis3"
|
||||||
run_dump_test "ima"
|
run_dump_test "ima"
|
||||||
|
run_dump_test "crypto"
|
||||||
|
|
||||||
run_list_test "pr4587" ""
|
run_list_test "pr4587" ""
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,5 +1,8 @@
|
|||||||
2012-04-27 David S. Miller <davem@davemloft.net>
|
2012-04-27 David S. Miller <davem@davemloft.net>
|
||||||
|
|
||||||
|
* sparc.h: Document new arg code' )' for crypto RS3
|
||||||
|
immediates.
|
||||||
|
|
||||||
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
|
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
|
||||||
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
|
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
|
||||||
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
|
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
|
||||||
|
|||||||
@ -224,6 +224,7 @@ typedef struct sparc_opcode
|
|||||||
_ Ancillary state register in rd (v9a)
|
_ Ancillary state register in rd (v9a)
|
||||||
/ Ancillary state register in rs1 (v9a)
|
/ Ancillary state register in rs1 (v9a)
|
||||||
( entire floating point state register (%efsr)
|
( entire floating point state register (%efsr)
|
||||||
|
) 5 bit immediate placed in RS3 field
|
||||||
= 2+8 bit PC relative immediate. (v9) */
|
= 2+8 bit PC relative immediate. (v9) */
|
||||||
|
|
||||||
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
|
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
|
||||||
|
|||||||
@ -1,5 +1,8 @@
|
|||||||
2012-04-27 David S. Miller <davem@davemloft.net>
|
2012-04-27 David S. Miller <davem@davemloft.net>
|
||||||
|
|
||||||
|
* sparc-dis.c (print_insn_sparc): Handle ')'.
|
||||||
|
* sparc-opc.c (sparc_opcodes): Add crypto instructions.
|
||||||
|
|
||||||
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
|
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
|
||||||
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
|
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
|
||||||
|
|
||||||
|
|||||||
@ -704,6 +704,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
|
|||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case ')': /* 5 bit unsigned immediate from RS3. */
|
||||||
|
(info->fprintf_func) (stream, "%#x", X_RS3 (insn));
|
||||||
|
break;
|
||||||
|
|
||||||
case 'X': /* 5 bit unsigned immediate. */
|
case 'X': /* 5 bit unsigned immediate. */
|
||||||
case 'Y': /* 6 bit unsigned immediate. */
|
case 'Y': /* 6 bit unsigned immediate. */
|
||||||
{
|
{
|
||||||
|
|||||||
@ -1907,6 +1907,35 @@ SLCBCC("cbnefr", 15),
|
|||||||
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
|
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
|
||||||
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
|
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
|
||||||
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
|
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
|
||||||
|
{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{ "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },
|
||||||
|
{ "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b },
|
||||||
|
{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b },
|
||||||
|
{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
||||||
|
{ "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
||||||
|
{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
||||||
|
{ "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b },
|
||||||
|
{ "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b },
|
||||||
|
{ "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b },
|
||||||
|
{ "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b },
|
||||||
|
{ "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b },
|
||||||
|
{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
|
||||||
|
{ "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
|
||||||
|
{ "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
|
||||||
|
{"aes_eround01", F2(2, 0x19)|OPF_LOW4(0), F2(~2, ~0x19)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_eround23", F2(2, 0x19)|OPF_LOW4(1), F2(~2, ~0x19)|OPF_LOW4(~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_dround01", F2(2, 0x19)|OPF_LOW4(2), F2(~2, ~0x19)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_dround23", F2(2, 0x19)|OPF_LOW4(3), F2(~2, ~0x19)|OPF_LOW4(~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_eround01_l",F2(2, 0x19)|OPF_LOW4(4), F2(~2, ~0x19)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_eround23_l",F2(2, 0x19)|OPF_LOW4(5), F2(~2, ~0x19)|OPF_LOW4(~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_dround01_l",F2(2, 0x19)|OPF_LOW4(6), F2(~2, ~0x19)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_dround23_l",F2(2, 0x19)|OPF_LOW4(7), F2(~2, ~0x19)|OPF_LOW4(~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"aes_kexpand1", F2(2, 0x19)|OPF_LOW4(8), F2(~2, ~0x19)|OPF_LOW4(~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
|
||||||
|
{"des_round", F2(2, 0x19)|OPF_LOW4(9), F2(~2, ~0x19)|OPF_LOW4(~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
|
||||||
|
{"kasumi_fl_xor", F2(2, 0x19)|OPF_LOW4(10), F2(~2, ~0x19)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
||||||
|
{"kasumi_fi_xor", F2(2, 0x19)|OPF_LOW4(11), F2(~2, ~0x19)|OPF_LOW4(~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
||||||
|
{"camellia_f", F2(2, 0x19)|OPF_LOW4(12), F2(~2, ~0x19)|OPF_LOW4(~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
||||||
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
||||||
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
||||||
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
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Reference in New Issue
Block a user