espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-22 19:09:31 +08:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Improve "bits undefined" diagnostics

Browse Source 
This commit improves internal error message
"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"
to display actual unused bits (excluding non-instruction bits).

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Exclude non-
	instruction bits from displaying internal diagnostics.
	Change error message slightly.
This commit is contained in:
Tsukasa OI
2022-06-28 19:07:52 +09:00
parent 83029f7ff5
commit 6b84c098e5
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gas/config/tc-riscv.c
View File

@ -1398,8 +1398,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
if (used_bits != required_bits) if (used_bits != required_bits)
{ {
as_bad (_("internal: bad RISC-V opcode " as_bad (_("internal: bad RISC-V opcode "
"(bits 0x%lx undefined): %s %s"), "(bits %#llx undefined or invalid): %s %s"),
~(unsigned long)(used_bits & required_bits), (unsigned long long)(used_bits ^ required_bits),
opc->name, opc->args); opc->name, opc->args);
return false; return false;
} }