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MIPS/GAS/testsuite: Implement individual MIPS16 ISA testing
Implement individual MIPS16 ISA GAS testing for the 32-bit and 64-bit
variants of the base MIPS16 and the MIPS16e ISA each.
gas/
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e' and `mips16' prefixes.
(run_list_test_arch): Likewise.
Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
`mips16e-32' and `mips16e-64' architectures. Update `rol64',
`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
accordingly.
* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
* testsuite/gas/mips/mips16e@loc-swap.d: New test.
This commit is contained in:
Maciej W. Rozycki
@ -1,3 +1,17 @@
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
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`mips16e' and `mips16' prefixes.
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(run_list_test_arch): Likewise.
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Rename `mips16' architecture to `mips16-32'. Add `mips16-64',
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`mips16e-32' and `mips16e-64' architectures. Update `rol64',
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`mips16e', `elf${el}-rel2' and `elf-rel4' test invocations
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accordingly.
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* testsuite/gas/mips/mips16e@branch-swap-3.d: New test.
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* testsuite/gas/mips/mips16e@branch-swap-4.d: New test.
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* testsuite/gas/mips/mips16e@loc-swap-dis.d: New test.
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* testsuite/gas/mips/mips16e@loc-swap.d: New test.
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* testsuite/gas/mips/loc-swap.s: Use zeros rather than NOPs for
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@ -324,6 +324,12 @@ proc run_dump_test_arch { name opts arch } {
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set proparch [lindex [mips_arch_properties $arch 0] 0]
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set prefixes [list ${proparch}@ ]
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if { [ string match "mips16e*" $proparch ] } {
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lappend prefixes mips16e@
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}
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if { [ string match "mips16*" $proparch ] } {
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lappend prefixes mips16@
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}
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if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
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lappend prefixes octeon@
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}
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@ -374,6 +380,12 @@ proc run_list_test_arch { name opts arch } {
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set testname "MIPS $name ([concat $opts [mips_arch_displayname $arch]])"
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set proparch [lindex [mips_arch_properties $arch 0] 0]
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set prefixes [list ${proparch}@ ]
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if { [ string match "mips16e*" $proparch ] } {
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lappend prefixes mips16e@
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}
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if { [ string match "mips16*" $proparch ] } {
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lappend prefixes mips16@
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}
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if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
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lappend prefixes octeon@
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}
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@ -470,8 +482,14 @@ mips_arch_create mips64r6 64 mips64r5 { mips32r6 ror } \
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{ -march=mips64r6 -mtune=mips64r6 --defsym r6=} \
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{ -mmips:isa64r6 } \
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{ mipsisa64r6-*-* mipsisa64r6el-*-* }
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mips_arch_create mips16 32 {} {} \
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{ -march=mips1 -mips16 } { -mmips:16 }
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mips_arch_create mips16-32 32 {} {} \
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{ -march=mips1 -mips16 } { -mmips:3000 }
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mips_arch_create mips16-64 64 mips16-32 {} \
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{ -march=mips3 -mips16 } { -mmips:4000 }
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mips_arch_create mips16e-32 32 mips16-32 {} \
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{ -march=mips32 -mips16 } { -mmips:isa32 }
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mips_arch_create mips16e-64 64 mips16-64 { mips16e-32 } \
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{ -march=mips64 -mips16 } { -mmips:isa64 }
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mips_arch_create micromips 64 mips64r2 {} \
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{ -march=mips64r2 -mmicromips } {}
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mips_arch_create r3000 32 mips1 {} \
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@ -820,7 +838,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "rol" [mips_arch_list_matching mips1 !ror]
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run_dump_test_arches "rol-hw" [mips_arch_list_matching ror]
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run_dump_test_arches "rol64" [mips_arch_list_matching gpr64 !ror]
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run_dump_test_arches "rol64" \
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[mips_arch_list_matching gpr64 !ror !mips16-32]
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run_dump_test_arches "rol64-hw" [mips_arch_list_matching gpr64 ror]
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run_dump_test "sb"
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@ -857,8 +876,7 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips16-macro-t" "{{as} {-march=mips3}}"
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run_dump_test "mips16-macro-e" "{{as} {-march=mips3}}"
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# Check MIPS16e extensions
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run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips \
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!mips32r6]
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run_dump_test_arches "mips16e" [mips_arch_list_matching mips16e-32]
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# Check jalx handling
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run_dump_test "mips16-jalx"
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run_dump_test "mips-jalx"
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@ -1074,10 +1092,11 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "mips-abi32-pic2"
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run_dump_test "elf${el}-rel"
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run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64 !singlefloat]
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run_dump_test_arches "elf${el}-rel2" \
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[mips_arch_list_matching gpr64 !singlefloat !mips16-32]
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run_dump_test "e32${el}-rel2"
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run_dump_test "elf${el}-rel3"
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run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
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run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64 !mips16-32]
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run_dump_test "e32-rel4"
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run_dump_test "elf-rel5"
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run_dump_test "elf-rel6"
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41
gas/testsuite/gas/mips/mips16e@branch-swap-3.d
Normal file
41
gas/testsuite/gas/mips/mips16e@branch-swap-3.d
Normal file
@ -0,0 +1,41 @@
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#objdump: -dr -M reg-names=numeric
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#as: -32 -O2 -aln=branch-swap-lst.lst
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#name: MIPS branch swapping with assembler listing
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#source: branch-swap-3.s
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# Check delay slot filling with a listing file works (MIPS16e)
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <test>:
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[ 0-9a-f]+: 1800 0000 jal 0 <test>
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[ ]*[0-9a-f]+: R_MIPS16_26 func
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[ 0-9a-f]+: 6702 move \$16,\$2
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[ 0-9a-f]+: 1800 0000 jal 0 <test>
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[ ]*[0-9a-f]+: R_MIPS16_26 func
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[ 0-9a-f]+: 4101 addiu \$16,\$17,1
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[ 0-9a-f]+: 4101 addiu \$16,\$17,1
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[ 0-9a-f]+: 1800 0000 jal 0 <test>
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[ ]*[0-9a-f]+: R_MIPS16_26 func
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: f7f7 410f addiu \$16,\$17,16383
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[ 0-9a-f]+: 1800 0000 jal 0 <test>
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[ ]*[0-9a-f]+: R_MIPS16_26 func
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: f7f7 410f addiu \$16,\$17,16383
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[ 0-9a-f]+: 1800 0000 jal 0 <test>
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[ ]*[0-9a-f]+: R_MIPS16_26 func
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[ 0-9a-f]+: 6500 nop
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[ 0-9a-f]+: e820 jr \$31
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[ 0-9a-f]+: 6702 move \$16,\$2
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[ 0-9a-f]+: e820 jr \$31
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[ 0-9a-f]+: 4101 addiu \$16,\$17,1
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[ 0-9a-f]+: 4101 addiu \$16,\$17,1
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[ 0-9a-f]+: e8a0 jrc \$31
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[ 0-9a-f]+: f7f7 410f addiu \$16,\$17,16383
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[ 0-9a-f]+: e8a0 jrc \$31
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[ 0-9a-f]+: f7f7 410f addiu \$16,\$17,16383
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[ 0-9a-f]+: e8a0 jrc \$31
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\.\.\.
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5
gas/testsuite/gas/mips/mips16e@branch-swap-4.d
Normal file
5
gas/testsuite/gas/mips/mips16e@branch-swap-4.d
Normal file
@ -0,0 +1,5 @@
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#objdump: -dr -M reg-names=numeric
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#as: -32 -O2
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#name: MIPS branch swapping without assembler listing
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#source: branch-swap-3.s
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#dump: mips16e@branch-swap-3.d
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30
gas/testsuite/gas/mips/mips16e@loc-swap-dis.d
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30
gas/testsuite/gas/mips/mips16e@loc-swap-dis.d
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@ -0,0 +1,30 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: MIPS DWARF-2 location information with branch swapping disassembly
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#as: -32
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#source: loc-swap.s
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# Check branch swapping with DWARF-2 location information (MIPS16e).
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 6790 move a0,s0
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[0-9a-f]+ <[^>]*> ec80 jrc a0
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[0-9a-f]+ <[^>]*> ec00 jr a0
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[0-9a-f]+ <[^>]*> 65f8 move ra,s0
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[0-9a-f]+ <[^>]*> e820 jr ra
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[0-9a-f]+ <[^>]*> 6790 move a0,s0
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[0-9a-f]+ <[^>]*> 65f8 move ra,s0
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[0-9a-f]+ <[^>]*> e8a0 jrc ra
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[0-9a-f]+ <[^>]*> 6790 move a0,s0
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[0-9a-f]+ <[^>]*> ecc0 jalrc a0
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[0-9a-f]+ <[^>]*> 65f8 move ra,s0
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[0-9a-f]+ <[^>]*> ecc0 jalrc a0
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[0-9a-f]+ <[^>]*> 1800 0000 jal 0+0000 <foo>
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[ ]*[0-9a-f]+: R_MIPS16_26 bar
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[0-9a-f]+ <[^>]*> 6790 move a0,s0
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[0-9a-f]+ <[^>]*> 65f8 move ra,s0
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[0-9a-f]+ <[^>]*> 1800 0000 jal 0+0000 <foo>
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[ ]*[0-9a-f]+: R_MIPS16_26 bar
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[0-9a-f]+ <[^>]*> 6500 nop
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\.\.\.
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61
gas/testsuite/gas/mips/mips16e@loc-swap.d
Normal file
61
gas/testsuite/gas/mips/mips16e@loc-swap.d
Normal file
@ -0,0 +1,61 @@
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#PROG: readelf
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#readelf: -wl
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#name: MIPS DWARF-2 location information with branch swapping
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#as: -32
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#source: loc-swap.s
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# Verify that DWARF-2 location information for instructions reordered
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# into a branch delay slot is updated to point to the branch instead.
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Raw dump of debug contents of section \.debug_line:
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Offset: 0x0
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Length: 67
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DWARF Version: 2
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Prologue Length: 33
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Minimum Instruction Length: 1
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Initial value of 'is_stmt': 1
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Line Base: -5
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Line Range: 14
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Opcode Base: 13
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Opcodes:
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Opcode 1 has 0 args
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Opcode 2 has 1 args
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Opcode 3 has 1 args
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Opcode 4 has 1 args
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Opcode 5 has 1 args
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Opcode 6 has 0 args
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Opcode 7 has 0 args
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Opcode 8 has 0 args
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Opcode 9 has 1 args
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Opcode 10 has 0 args
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Opcode 11 has 0 args
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Opcode 12 has 1 args
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The Directory Table is empty\.
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The File Name Table \(offset 0x.*\):
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Entry Dir Time Size Name
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1 0 0 0 loc-swap\.s
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Line Number Statements:
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\[0x.*\] Extended opcode 2: set Address to 0x1
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\[0x.*\] Special opcode 11: advance Address by 0 to 0x1 and Line by 6 to 7
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\[0x.*\] Special opcode 35: advance Address by 2 to 0x3 and Line by 2 to 9
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\[0x.*\] Special opcode 36: advance Address by 2 to 0x5 and Line by 3 to 12
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\[0x.*\] Special opcode 7: advance Address by 0 to 0x5 and Line by 2 to 14
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\[0x.*\] Special opcode 64: advance Address by 4 to 0x9 and Line by 3 to 17
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\[0x.*\] Special opcode 7: advance Address by 0 to 0x9 and Line by 2 to 19
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\[0x.*\] Special opcode 64: advance Address by 4 to 0xd and Line by 3 to 22
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\[0x.*\] Special opcode 35: advance Address by 2 to 0xf and Line by 2 to 24
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\[0x.*\] Special opcode 36: advance Address by 2 to 0x11 and Line by 3 to 27
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\[0x.*\] Special opcode 35: advance Address by 2 to 0x13 and Line by 2 to 29
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\[0x.*\] Special opcode 36: advance Address by 2 to 0x15 and Line by 3 to 32
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\[0x.*\] Special opcode 35: advance Address by 2 to 0x17 and Line by 2 to 34
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\[0x.*\] Special opcode 36: advance Address by 2 to 0x19 and Line by 3 to 37
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\[0x.*\] Special opcode 7: advance Address by 0 to 0x19 and Line by 2 to 39
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\[0x.*\] Special opcode 92: advance Address by 6 to 0x1f and Line by 3 to 42
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\[0x.*\] Special opcode 35: advance Address by 2 to 0x21 and Line by 2 to 44
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\[0x.*\] Advance PC by 31 to 0x40
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\[0x.*\] Extended opcode 1: End of Sequence
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