espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-18 08:38:10 +08:00
Code Issues Packages Projects Releases Wiki Activity

CSKY: Change mvtc and mulsw's ISA flag.

Browse Source 
gas/
	* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
	(CSKY_ISA_860): Likewise.

include/
	* opcode/csky.h (CSKY_ISA_DSPE60): Define.

opcodes/
	* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
	ISA flag.
This commit is contained in:
Cooper Qu
2020-09-07 17:25:14 +08:00
committed by Lifang Xia
parent a2061b9f29
commit 6a1ed9106f
6 changed files with 19 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
(CSKY_ISA_860): Likewise.
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* config/tc-csky.c (float_abi): New. * config/tc-csky.c (float_abi): New.

4
gas/config/tc-csky.c
View File

@ -611,7 +611,7 @@ const struct csky_cpu_info csky_cpus[] =
/* CK801 series. */ /* CK801 series. */
#define CSKY_ISA_801 CSKYV2_ISA_E1 #define CSKY_ISA_801 CSKYV2_ISA_E1
#define CSKYV2_ISA_DSP (CSKY_ISA_DSP | CSKY_ISA_DSP_1E2) #define CSKYV2_ISA_DSP (CSKY_ISA_DSP | CSKY_ISA_DSP_1E2 | CSKY_ISA_DSPE60)
{"ck801", CSKY_ARCH_801, CSKY_ISA_801}, {"ck801", CSKY_ARCH_801, CSKY_ISA_801},
{"ck801t", CSKY_ARCH_801, CSKY_ISA_801 | CSKY_ISA_TRUST}, {"ck801t", CSKY_ARCH_801, CSKY_ISA_801 | CSKY_ISA_TRUST},
@ -708,7 +708,7 @@ const struct csky_cpu_info csky_cpus[] =
{"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST}, {"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST},
/* CK860 Series. */ /* CK860 Series. */
#define CSKY_ISA_860 (CSKY_ISA_810 | CSKYV2_ISA_10E60 | CSKYV2_ISA_3E3R3) #define CSKY_ISA_860 (CSKY_ISA_810 | CSKYV2_ISA_10E60 | CSKYV2_ISA_3E3R3 | CSKY_ISA_DSPE60)
#define CSKY_ISA_860F (CSKY_ISA_860 | CSKY_ISA_FLOAT_7E60) #define CSKY_ISA_860F (CSKY_ISA_860 | CSKY_ISA_FLOAT_7E60)
{"ck860", CSKY_ARCH_860, CSKY_ISA_860}, {"ck860", CSKY_ARCH_860, CSKY_ISA_860},
{"ck860f", CSKY_ARCH_860, CSKY_ISA_860F}, {"ck860f", CSKY_ARCH_860, CSKY_ISA_860F},

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* opcode/csky.h (CSKY_ISA_DSPE60): Define.
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define. * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.

1
include/opcode/csky.h
View File

@ -47,6 +47,7 @@
#define CSKY_ISA_DSP (1L << 20) #define CSKY_ISA_DSP (1L << 20)
#define CSKY_ISA_DSP_1E2 (1L << 21) #define CSKY_ISA_DSP_1E2 (1L << 21)
#define CSKY_ISA_DSP_ENHANCE (1L << 22) #define CSKY_ISA_DSP_ENHANCE (1L << 22)
#define CSKY_ISA_DSPE60 (1L << 23)
/* Base float instruction (803f & 810f). */ /* Base float instruction (803f & 810f). */
#define CSKY_ISA_FLOAT_E1 (1L << 25) #define CSKY_ISA_FLOAT_E1 (1L << 25)

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
ISA flag.
2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-dis.c (csky_output_operand): Add handlers for * csky-dis.c (csky_output_operand): Add handlers for

4
opcodes/csky-opc.h
View File

@ -2687,7 +2687,7 @@ const struct csky_opcode csky_v2_opcodes[] =
CSKY_ISA_DSP), CSKY_ISA_DSP),
OP32 ("mvtc", OP32 ("mvtc",
OPCODE_INFO0 (0xc4009a00), OPCODE_INFO0 (0xc4009a00),
CSKY_ISA_DSP), CSKY_ISA_DSPE60),
OP32 ("mfhi", OP32 ("mfhi",
OPCODE_INFO1 (0xc4009c20, OPCODE_INFO1 (0xc4009c20,
(0_4, AREG, OPRND_SHIFT_0_BIT)), (0_4, AREG, OPRND_SHIFT_0_BIT)),
@ -4119,7 +4119,7 @@ const struct csky_opcode csky_v2_opcodes[] =
OPCODE_INFO2 (0xc4009420, OPCODE_INFO2 (0xc4009420,
(0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT),
(21_25, AREG, OPRND_SHIFT_0_BIT)), (21_25, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP), CSKY_ISA_DSPE60),
OP16_OP32 ("ld.b", OP16_OP32 ("ld.b",
SOPCODE_INFO2 (0x8000, SOPCODE_INFO2 (0x8000,
(5_7, GREG0_7, OPRND_SHIFT_0_BIT), (5_7, GREG0_7, OPRND_SHIFT_0_BIT),