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x86: correct UDn

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Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.

Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.

For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
This commit is contained in:
Jan Beulich
2017-11-23 10:59:48 +01:00
committed by Jan Beulich
parent 38bf51134d
commit 66f1eba0b7
13 changed files with 68 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
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@ -1,3 +1,12 @@
2017-11-23 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0.
* testsuite/gas/i386/intel.s: Test ud2 instead of ud2b.
* testsuite/gas/i386/opcode.s: Likewise.
* testsuite/gas/i386/arch-4.d, testsuite/gas/i386/intel.d,
testsuite/gas/i386/opcode.d, testsuite/gas/i386/opcode-intel.d,
testsuite/gas/i386/opcode-suffix.d: Adjust expectations.
2017-11-23 Jan Beulich <jbeulich@suse.com> 2017-11-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Don't call * config/tc-i386-intel.c (i386_intel_operand): Don't call

6
gas/testsuite/gas/i386/arch-4.d
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@ -1,4 +1,3 @@
#as: -march=generic32
#objdump: -dw #objdump: -dw
#name: i386 arch 4 #name: i386 arch 4
@ -7,8 +6,9 @@
Disassembly of section .text: Disassembly of section .text:
0+ <.text>: 0+ <.text>:
[ ]*[a-f0-9]+: 0f b9 ud1 [ ]*[a-f0-9]+: 0f ff 07 [ ]*ud0 \(%edi\),%eax
[ ]*[a-f0-9]+: 0f b9 07 [ ]*ud1 \(%edi\),%eax
[ ]*[a-f0-9]+: 0f 0b ud2 [ ]*[a-f0-9]+: 0f 0b ud2
[ ]*[a-f0-9]+: 0f 0b ud2 [ ]*[a-f0-9]+: 0f 0b ud2
[ ]*[a-f0-9]+: 0f b9 ud1 [ ]*[a-f0-9]+: 0f b9 07 [ ]*ud1 \(%edi\),%eax
#pass #pass

5
gas/testsuite/gas/i386/arch-4.s
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@ -1,5 +1,6 @@
.text .text
ud1 ud0 (%edi),%eax
ud1 (%edi),%eax
ud2 ud2
ud2a ud2a
ud2b ud2b (%edi),%eax

2
gas/testsuite/gas/i386/intel.d
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@ -360,7 +360,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f b9 [ ]*ud1 [ ]*[a-f0-9]+: 0f 0b [ ]*ud2[ ]*
[ ]*[a-f0-9]+: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\) [ ]*[a-f0-9]+: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx [ ]*[a-f0-9]+: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx

2
gas/testsuite/gas/i386/intel.s
View File

@ -353,7 +353,7 @@ foo:
lgs edx, 0x90909090[eax] lgs edx, 0x90909090[eax]
movzx edx, byte ptr 0x90909090[eax] movzx edx, byte ptr 0x90909090[eax]
movzx edx, word ptr 0x90909090[eax] movzx edx, word ptr 0x90909090[eax]
ud2b ud2
btc 0x90909090[eax], edx btc 0x90909090[eax], edx
bsf edx, 0x90909090[eax] bsf edx, 0x90909090[eax]
bsr edx, 0x90909090[eax] bsr edx, 0x90909090[eax]

2
gas/testsuite/gas/i386/opcode-intel.d
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@ -358,7 +358,7 @@ Disassembly of section .text:
*[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgs[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] *[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgs[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
*[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzx[ ]+edx,BYTE PTR \[eax-0x6f6f6f70\] *[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzx[ ]+edx,BYTE PTR \[eax-0x6f6f6f70\]
*[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzx[ ]+edx,WORD PTR \[eax-0x6f6f6f70\] *[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzx[ ]+edx,WORD PTR \[eax-0x6f6f6f70\]
*[0-9a-f]+: 0f b9[ ]+ud1[ ]* *[0-9a-f]+: 0f 0b[ ]+ud2[ ]*
*[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btc[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx *[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btc[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
*[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsf[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] *[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsf[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
*[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsr[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] *[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsr[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]

2
gas/testsuite/gas/i386/opcode-suffix.d
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@ -358,7 +358,7 @@ Disassembly of section .text:
*[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgsl[ ]+-0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgsl[ ]+-0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzbl -0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzbl -0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzwl -0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzwl -0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f b9[ ]+ud1[ ]+ *[0-9a-f]+: 0f 0b[ ]+ud2[ ]*
*[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btcl[ ]+%edx,-0x6f6f6f70\(%eax\) *[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btcl[ ]+%edx,-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsfl[ ]+-0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsfl[ ]+-0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsrl[ ]+-0x6f6f6f70\(%eax\),%edx *[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsrl[ ]+-0x6f6f6f70\(%eax\),%edx

2
gas/testsuite/gas/i386/opcode.d
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@ -357,7 +357,7 @@ Disassembly of section .text:
57e: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx 57e: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx
585: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx 585: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx
58c: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx 58c: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx
593: 0f b9 [ ]*ud1 593: 0f 0b [ ]*ud2[ ]*
595: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\) 595: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\)
59c: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx 59c: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx
5a3: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx 5a3: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx

2
gas/testsuite/gas/i386/opcode.s
View File

@ -350,7 +350,7 @@ foo:
lgs 0x90909090(%eax),%edx lgs 0x90909090(%eax),%edx
movzbl 0x90909090(%eax),%edx movzbl 0x90909090(%eax),%edx
movzwl 0x90909090(%eax),%edx movzwl 0x90909090(%eax),%edx
ud2b ud2
btc %edx,0x90909090(%eax) btc %edx,0x90909090(%eax)
bsf 0x90909090(%eax),%edx bsf 0x90909090(%eax),%edx
bsr 0x90909090(%eax),%edx bsr 0x90909090(%eax),%edx

8
opcodes/ChangeLog
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@ -1,3 +1,11 @@
2017-11-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
(twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
* i386-opc.tbl (ud1, ud2b): Add operands.
(ud0): New.
* i386-tbl.h: Re-generate.
2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com> 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb. * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.

8
opcodes/i386-dis.c
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@ -3067,7 +3067,7 @@ static const struct dis386 dis386_twobyte[] = {
{ "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
/* b8 */ /* b8 */
{ PREFIX_TABLE (PREFIX_0FB8) }, { PREFIX_TABLE (PREFIX_0FB8) },
{ "ud1", { XX }, 0 }, { "ud1S", { Gv, Ev }, 0 },
{ REG_TABLE (REG_0FBA) }, { REG_TABLE (REG_0FBA) },
{ "btcS", { Evh1, Gv }, 0 }, { "btcS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FBC) }, { PREFIX_TABLE (PREFIX_0FBC) },
@ -3145,7 +3145,7 @@ static const struct dis386 dis386_twobyte[] = {
{ "paddb", { MX, EM }, PREFIX_OPCODE }, { "paddb", { MX, EM }, PREFIX_OPCODE },
{ "paddw", { MX, EM }, PREFIX_OPCODE }, { "paddw", { MX, EM }, PREFIX_OPCODE },
{ "paddd", { MX, EM }, PREFIX_OPCODE }, { "paddd", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode }, { "ud0S", { Gv, Ev }, 0 },
}; };
static const unsigned char onebyte_has_modrm[256] = { static const unsigned char onebyte_has_modrm[256] = {
@ -3185,11 +3185,11 @@ static const unsigned char twobyte_has_modrm[256] = {
/* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
/* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
/* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
/* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
/* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
/* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
/* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
/* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
/* ------------------------------- */ /* ------------------------------- */
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
}; };

6
opcodes/i386-opc.tbl
View File

@ -861,9 +861,11 @@ ud2, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
// alias for ud2 // alias for ud2
ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// 2nd. official undefined instr. // 2nd. official undefined instr.
ud1, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } ud1, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
// alias for ud1 // alias for ud1
ud2b, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } ud2b, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
// 3rd official undefined instr (older CPUs don't take a ModR/M byte)
ud0, 2, 0xfff, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
cmovo, 2, 0xf40, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } cmovo, 2, 0xf40, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
cmovno, 2, 0xf41, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } cmovno, 2, 0xf41, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }

39
opcodes/i386-tbl.h
View File

@ -9579,32 +9579,55 @@ const insn_template i386_optab[] =
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
{ "ud1", 0, 0xfb9, None, 2, { "ud1", 2, 0xfb9, None, 2,
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } }, 0, 0, 0 } },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
{ "ud2b", 0, 0xfb9, None, 2, { "ud2b", 2, 0xfb9, None, 2,
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0 } }, 0, 0, 0 } },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0 }, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ "ud0", 2, 0xfff, None, 2,
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 },
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{ "cmovo", 2, 0xf40, None, 2, { "cmovo", 2, 0xf40, None, 2,