RISC-V: Support rvv extension with released version 1.0.

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2021-11-17  Jim Wilson  <jimw@sifive.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x

And here is the vector spec,
https://github.com/riscv/riscv-v-spec

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
	of v, zve and zvl extensions.
	(riscv_supported_std_ext): Updated verison of v to  1.0.
	(riscv_supported_std_z_ext): Added zve and zvl extensions.
	(riscv_parse_check_conflicts): The zvl extensions need to
	enable either v or zve extension.
	(riscv_multi_subset_supports): Check the subset list to know
	if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported.
gas/
	* config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V.
	(enum reg_class): Added RCLASS_VECR and RCLASS_VECM.
	(validate_riscv_insn): Check whether the rvv operands are valid.
	(md_begin): Initialize register hash for rvv registers.
	(macro_build): Added rvv operands when expanding rvv pseudoes.
	(vector_macro): Expand rvv macros into one or more instructions.
	(macro): Likewise.
	(my_getVsetvliExpression): Similar to my_getVsetvliExpression,
	but used for parsing vsetvli operands.
	(riscv_ip): Parse and encode rvv operands.  Besides, The rvv loads
	and stores with EEW 64 cannot be used when zve32x is enabled.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march
	to rv32ifv_zkr.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/march-imply-v.d: New testcase.
	* testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise.
	* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise.
	* testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise.
	* testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise.
	* testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise.
	* testsuite/gas/riscv/vector-insns.d: Likewise.
	* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
	* opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv.
	* opcode/riscv.h: Defined rvv immediate encodings and fields.
	(enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF.
	(INSN_V_EEW64): Defined.
	(M_VMSGE, M_VMSGEU): Added for the rvv pseudoes.
opcodes/
	* riscv-dis.c (print_insn_args): Dump the rvv operands.
	* riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers.
	(riscv_vecm_names_numeric): Likewise.
	(riscv_vsew): Likewise.
	(riscv_vlmul): Likewise.
	(riscv_vta): Likewise.
	(riscv_vma): Likewise.
	(match_vs1_eq_vs2): Added for rvv Vu operand.
	(match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand.
	(riscv_opcodes): Added rvv v1.0 instructions.

...

This commit is contained in:

Nelson Chu

2021-11-17 18:46:11 +08:00

parent 486f9e20e0

commit 65e4a99a26

24 changed files with 6615 additions and 15 deletions

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include/opcode/riscv-opc.h

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