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* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8

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for bset, bclr, btst instructions.
        (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
This commit is contained in:
Jeff Law
1996-11-06 21:18:27 +00:00
parent a28b95d71d
commit 64ce06688d
2 changed files with 20 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
opcodes/ChangeLog
View File

@ -1,5 +1,9 @@
Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
for bset, bclr, btst instructions.
(mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
* mn10300-opc.c (mn10300_operands): Remove many redundant * mn10300-opc.c (mn10300_operands): Remove many redundant
operands. Update opcode table as appropriate. operands. Update opcode table as appropriate.
(IMM32): Add MN10300_OPERAND_SPLIT flag. (IMM32): Add MN10300_OPERAND_SPLIT flag.

19
opcodes/mn10300-opc.c
View File

@ -65,10 +65,18 @@ const struct mn10300_operand mn10300_operands[] = {
#define IMM16 (IMM8+1) #define IMM16 (IMM8+1)
{16, 0, MN10300_OPERAND_PROMOTE}, {16, 0, MN10300_OPERAND_PROMOTE},
/* 32bit immediate, high 16 bits in the main instruction
word, 16bits in the extension word. */
#define IMM32 (IMM16+1) #define IMM32 (IMM16+1)
{32, 0, MN10300_OPERAND_SPLIT}, {32, 0, MN10300_OPERAND_SPLIT},
#define SP (IMM32+1) /* 32bit immediate, high 16 bits in the main instruction
word, 16bits in the extension word, low 16bits are left
shifted 8 places. */
#define IMM32_LOWSHIFT8 (IMM32+1)
{32, 8, MN10300_OPERAND_SPLIT},
#define SP (IMM32_LOWSHIFT8+1)
{8, 0, MN10300_OPERAND_SP}, {8, 0, MN10300_OPERAND_SP},
#define PSW (SP+1) #define PSW (SP+1)
@ -313,15 +321,18 @@ const struct mn10300_opcode mn10300_opcodes[] = {
{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}}, { "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, { "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, { "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8, MEM(IMM32)}}, { "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
MEM(IMM32_LOWSHIFT8)}},
{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, { "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
{IMM8, MEM2(SD8N_SHIFT8,AN0)}}, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8, MEM(IMM32)}}, { "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
MEM(IMM32_LOWSHIFT8)}},
{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, { "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
{IMM8, MEM2(SD8N_SHIFT8,AN0)}}, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(IMM32)}}, { "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
MEM(IMM32_LOWSHIFT8)}},
{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, { "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
MEM2(SD8N_SHIFT8,AN0)}}, MEM2(SD8N_SHIFT8,AN0)}},