Add support for M340 processor

sim/mcore/ChangeLog

@@ -1,3 +1,10 @@
+2000-02-10  Nick Clifton  <nickc@cygnus.com>
+
+	* interp.c (target_big_endian): New variable.
+	(mcore_extract_unsigned_integer, mcore_store_unsigned_integer,
+	wlat, rlat, sim_resume, sim_load): Add supprot for little
+	endian targets. 
+
 2000-01-13  Nick Clifton  <nickc@cygnus.com>
 
 	* interp.c (sim_resume): Do not rely upon host semantics of shift

sim/mcore/interp.c

@@ -1,5 +1,5 @@
 /* Simulator for Motorola's MCore processor
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
    Contributed by Cygnus Solutions.
 
 This file is part of GDB, the GNU debugger.
@@ -36,6 +36,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 typedef long int           word;
 typedef unsigned long int  uword;
 
+static int            target_big_endian = 0;
 static unsigned long  heap_ptr = 0;
 host_callback *       callback;
 
@@ -58,6 +59,12 @@ mcore_extract_unsigned_integer (addr, len)
      the least significant.  */
   retval = 0;
 
+  if (! target_big_endian)
+    {
+      for (p = endaddr; p > startaddr;)
+	retval = (retval << 8) | * -- p;
+    }
+  else
     {
       for (p = startaddr; p < endaddr;)
 	retval = (retval << 8) | * p ++;
@@ -76,6 +83,15 @@ mcore_store_unsigned_integer (addr, len, val)
   unsigned char * startaddr = (unsigned char *)addr;
   unsigned char * endaddr = startaddr + len;
 
+  if (! target_big_endian)
+    {
+      for (p = startaddr; p < endaddr;)
+	{
+	  * p ++ = val & 0xff;
+	  val >>= 8;
+	}
+    }
+  else
     {
       for (p = endaddr; p > startaddr;)
 	{
@@ -92,7 +108,7 @@ mcore_store_unsigned_integer (addr, len, val)
    Keeping this data in target byte order simplifies the register
    read/write functions.  Keeping this data in native order improves
    the performance of the simulator.  Simulation speed is deemed more
-   important. */
+   important.  */
 
 /* The ordering of the mcore_regset structure is matched in the
    gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro.  */
@@ -216,6 +232,14 @@ wlat (x, v)
       
 	  cpu.asregs.exception = SIGBUS;
 	}
+      else if (! target_big_endian)
+	{
+	  unsigned char * p = cpu.mem + x;
+	  p[3] = v >> 24;
+	  p[2] = v >> 16;
+	  p[1] = v >> 8;
+	  p[0] = v;
+	}
       else
 	{
 	  unsigned char * p = cpu.mem + x;
@@ -248,6 +272,12 @@ what (x, v)
       
 	  cpu.asregs.exception = SIGBUS;
 	}
+      else if (! target_big_endian)
+	{
+	  unsigned char * p = cpu.mem + x;
+	  p[1] = v >> 8;
+	  p[0] = v;
+	}
       else
 	{
 	  unsigned char * p = cpu.mem + x;
@@ -299,6 +329,11 @@ rlat (x)
 	  cpu.asregs.exception = SIGBUS;
 	  return 0;
 	}
+      else if (! target_big_endian)
+	{
+	  unsigned char * p = cpu.mem + x;
+	  return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
+	}
       else
 	{
 	  unsigned char * p = cpu.mem + x;
@@ -329,6 +364,11 @@ rhat (x)
 	  cpu.asregs.exception = SIGBUS;
 	  return 0;
 	}
+      else if (! target_big_endian)
+	{
+	  unsigned char * p = cpu.mem + x;
+	  return (p[1] << 8) | p[0];
+	}
       else
 	{
 	  unsigned char * p = cpu.mem + x;
@@ -762,11 +802,17 @@ sim_resume (sd, step, siggnal)
       
       if (pc & 02)
 	{
+	  if (! target_big_endian)
+	    inst = ibuf >> 16;
+	  else
 	    inst = ibuf & 0xFFFF;
 	  needfetch = 1;
 	}
       else
 	{
+	  if (! target_big_endian)
+	    inst = ibuf & 0xFFFF;
+	  else
 	    inst = ibuf >> 16;
 	}
 
@@ -1952,6 +1998,7 @@ sim_load (sd, prog, abfd, from_tty)
   if (prog_bfd == NULL)
     return SIM_RC_FAIL;
   
+  target_big_endian = bfd_big_endian (prog_bfd);
     
   if (abfd == NULL)
     bfd_close (prog_bfd);