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* Fixes for PRs 17559, 16602, brought over from sky branch.

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start-sanitize-r5900
Fri Oct 23 12:06:00 EDT 1998  Frank Ch. Eigler <fche@cygnus.com>
	* mips-opc.c (vrget, vclipw, vrnext): Correct COP2 opcodes
	and masks.
end-sanitize-r5900
This commit is contained in:
Frank Ch. Eigler
1998-10-23 11:31:32 +00:00
parent 24b2f07acf
commit 62c0e5bc39
2 changed files with 38 additions and 3 deletions
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35
opcodes/ChangeLog
View File

@ -1,4 +1,39 @@
start-sanitize-r5900
Fri Oct 23 12:06:00 EDT 1998 Frank Ch. Eigler <fche@cygnus.com>
* mips-opc.c (vrget, vclipw, vrnext): Correct COP2 opcodes
and masks.
end-sanitize-r5900
Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com>
start-sanitize-cygnus
* cgen-asm.in (insert_1): New function.
(insert_normal): Progress on handling ! CGEN_INT_INSN_P.
(insert_insn_normal): Update handling of CGEN_INT_INSN_P.
(@arch@_cgen_assemble_insn): Update type of `buf' arg.
* cgen-dis.in (extract_1): New function.
(extract_normal): buf_ctrl renamed to ex_info, update type.
Progress on handling of CGEN_INT_INSN_P.
(extract_insn_normal): buf_ctrl renamed to ex_info, update type.
Update handling of CGEN_INT_INSN_P. Handle errors from
@arch@_cgen_extract_operand.
(print_insn): Renamed from print_int_insn. Handle ! CGEN_INT_INSN_P.
(default_print_insn): Renamed from print_insn.
Handle ! CGEN_INT_INSN_P.
(print_insn_@arch@): Handle error returns from print_insn.
* cgen-opc.in (cgen_get_insn_value, cgen_put_insn_value): New fns.
(@arch@_cgen_lookup_insn): Update handling of CGEN_INT_INSN_P.
(@arch@_cgen_lookup_get_insn_operands): Ditto.
end-sanitize-cygnus
* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
start-sanitize-am33 start-sanitize-am33
Wed Oct 14 12:12:25 1998 Jeffrey A Law (law@cygnus.com)
* m10300-opc.c: Allow autoincrement stores using the same register
for source and destination operands.
Mon Oct 12 10:43:51 1998 Jeffrey A Law (law@cygnus.com) Mon Oct 12 10:43:51 1998 Jeffrey A Law (law@cygnus.com)
* m10300-opc.c: DSP instrutions which only write to one general * m10300-opc.c: DSP instrutions which only write to one general

6
opcodes/mips-opc.c
View File

@ -172,7 +172,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"vaddaz", "&UK,2K,1#z", 0x4a00003e, 0xfe0007ff, 0, T5}, {"vaddaz", "&UK,2K,1#z", 0x4a00003e, 0xfe0007ff, 0, T5},
{"vcallms","O", 0x4a000038, 0xffe0003f, 0, T5}, {"vcallms","O", 0x4a000038, 0xffe0003f, 0, T5},
{"vcallmsr", "9", 0x4a00d839, 0xffffffff, 0, T5}, {"vcallmsr", "9", 0x4a00d839, 0xffffffff, 0, T5},
{"vclip","2", 0x4be001ff, 0xffff07ff, 0, T5}, {"vclipw","&2K,1#w", 0x4a0001ff, 0xfe0007ff, 0, T5},
{"vdiv","Q,8,7", 0x4a0003bc, 0xfe0007ff, 0, T5}, {"vdiv","Q,8,7", 0x4a0003bc, 0xfe0007ff, 0, T5},
{"vftoi0", "&1K,2K", 0x4a00017c, 0xfe0007ff, 0, T5}, {"vftoi0", "&1K,2K", 0x4a00017c, 0xfe0007ff, 0, T5},
{"vftoi4", "&1K,2K", 0x4a00017d, 0xfe0007ff, 0, T5}, {"vftoi4", "&1K,2K", 0x4a00017d, 0xfe0007ff, 0, T5},
@ -258,9 +258,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"vnop","", 0x4a0002ff, 0xffffffff, 0, T5}, {"vnop","", 0x4a0002ff, 0xffffffff, 0, T5},
{"vopmula", ";UK,2K,1K", 0x4bc002fe, 0xffe007ff, 0, T5}, {"vopmula", ";UK,2K,1K", 0x4bc002fe, 0xffe007ff, 0, T5},
{"vopmsub", ";3K,2K,1K", 0x4bc0002e, 0xffe0003f, 0, T5}, {"vopmsub", ";3K,2K,1K", 0x4bc0002e, 0xffe0003f, 0, T5},
{"vrget", "&1K,X", 0x4a20043d, 0xfe00ffff, 0, T5}, {"vrget", "&1K,X", 0x4a00043d, 0xfe00ffff, 0, T5},
{"vrinit", "X,8", 0x4a00043e, 0xff9f07ff, 0, T5}, {"vrinit", "X,8", 0x4a00043e, 0xff9f07ff, 0, T5},
{"vrnext", "&1K,X", 0x4a20043c, 0xfe00ffff, 0, T5}, {"vrnext", "&1K,X", 0x4a00043c, 0xfe00ffff, 0, T5},
{"vrsqrt","Q,8,7", 0x4a0003be, 0xfe0007ff, 0, T5}, {"vrsqrt","Q,8,7", 0x4a0003be, 0xfe0007ff, 0, T5},
{"vrxor", "X,8", 0x4a00043f, 0xff9f07ff, 0, T5}, {"vrxor", "X,8", 0x4a00043f, 0xff9f07ff, 0, T5},
{"vsqd", "&2K,(--4)K", 0x4a00037f, 0xfe0007ff, 0, T5}, {"vsqd", "&2K,(--4)K", 0x4a00037f, 0xfe0007ff, 0, T5},