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IBM Z: Add missing vector formats to .insn docs

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	* doc/c-s390.texi: Document vector instruction formats.
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Andreas Krebbel
2021-02-03 12:01:12 +01:00
parent f01fb44c06
commit 61ecbbae8e
2 changed files with 53 additions and 1 deletions
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@ -1,3 +1,7 @@
2021-02-03 Andreas Krebbel <krebbel@linux.ibm.com>
* doc/c-s390.texi: Document vector instruction formats.
2021-02-01 Emery Hemingway <ehmry@posteo.net> 2021-02-01 Emery Hemingway <ehmry@posteo.net>
* configure.tgt: Add *-*-genode* as a target for AArch64 and x86. * configure.tgt: Add *-*-genode* as a target for AArch64 and x86.

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@ -312,7 +312,7 @@ field. The notation changes as follows:
@cindex instruction formats, s390 @cindex instruction formats, s390
@cindex s390 instruction formats @cindex s390 instruction formats
The Principles of Operation manuals lists 26 instruction formats where The Principles of Operation manuals lists 35 instruction formats where
some of the formats have multiple variants. For the @samp{.insn} some of the formats have multiple variants. For the @samp{.insn}
pseudo directive the assembler recognizes some of the formats. pseudo directive the assembler recognizes some of the formats.
Typically, the most general variant of the instruction format is used Typically, the most general variant of the instruction format is used
@ -544,6 +544,54 @@ with the @samp{.insn} pseudo directive:
0 8 12 16 20 32 36 47 0 8 12 16 20 32 36 47
@end verbatim @end verbatim
@item VRV format: <insn> V1,D2(V2,B2),M3
@verbatim
+--------+----+----+----+-------------+----+------------+
| OpCode | V1 | V2 | B2 | D2 | M3 | Opcode |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
@item VRI format: <insn> V1,V2,I3,M4,M5
@verbatim
+--------+----+----+-------------+----+----+------------+
| OpCode | V1 | V2 | I3 | M5 | M4 | Opcode |
+--------+----+----+-------------+----+----+------------+
0 8 12 16 28 32 36 47
@end verbatim
@item VRX format: <insn> V1,D2(R2,B2),M3
@verbatim
+--------+----+----+----+-------------+----+------------+
| OpCode | V1 | R2 | B2 | D2 | M3 | Opcode |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
@item VRS format: <insn> R1,V3,D2(B2),M4
@verbatim
+--------+----+----+----+-------------+----+------------+
| OpCode | R1 | V3 | B2 | D2 | M4 | Opcode |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
@item VRR format: <insn> V1,V2,V3,M4,M5,M6
@verbatim
+--------+----+----+----+---+----+----+----+------------+
| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode |
+--------+----+----+----+---+----+----+----+------------+
0 8 12 16 24 28 32 36 47
@end verbatim
@item VSI format: <insn> V1,D2(B2),I3
@verbatim
+--------+---------+----+-------------+----+------------+
| OpCode | I3 | B2 | D2 | V1 | Opcode |
+--------+---------+----+-------------+----+------------+
0 8 16 20 32 36 47
@end verbatim
@end table @end table
For the complete list of all instruction format variants see the For the complete list of all instruction format variants see the