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[PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul

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gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): New operands.
	(parse_operands): Handle new operands.
	(do_mve_vcmul): New encoding function.
	(do_vcmla): Change to support MVE variants.
	(do_vcadd): Change to support MVE variants.
	(insns): Change existing to support MVE variants and add new.
	* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
	* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
	* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
	* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
	* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
	* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
	* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
	* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
	* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
	* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
	* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
	* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
	* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
	* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
	* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
	* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
	* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
	* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
This commit is contained in:
Andre Vieira
2019-05-15 18:21:32 +01:00
parent f601a00c4c
commit 5d281bf033
20 changed files with 350 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
gas/ChangeLog
View File

@ -1,3 +1,30 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(do_mve_vcmul): New encoding function.
(do_vcmla): Change to support MVE variants.
(do_vcadd): Change to support MVE variants.
(insns): Change existing to support MVE variants and add new.
* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.

133
gas/config/tc-arm.c
View File

@ -6951,6 +6951,7 @@ enum operand_parse_code
OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
*/
OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
OP_VMOV, /* Neon VMOV operands. */
OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
@ -7346,6 +7347,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
}
break;
case OP_RNDQMQ_RNSC:
po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
break;
try_rndq_rnsc:
case OP_RNDQ_RNSC:
{
po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
@ -15574,6 +15579,38 @@ do_mve_vcmp (void)
return;
}
static void
do_mve_vcmul (void)
{
enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
unsigned rot = inst.relocs[0].exp.X_add_number;
constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
_("immediate out of range"));
if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
|| inst.operands[0].reg == inst.operands[2].reg))
as_tsktsk (BAD_MVE_SRCDEST);
inst.instruction |= (et.size == 32) << 28;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= (rot > 90) << 12;
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= LOW4 (inst.operands[2].reg);
inst.instruction |= (rot == 90 || rot == 270);
inst.is_neon = 1;
}
static void
do_vfp_nsyn_cmp (void)
{
@ -19677,16 +19714,23 @@ neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
static void
do_vcmla (void)
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
_(BAD_FPU));
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
&& (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
|| !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
unsigned rot = inst.relocs[0].exp.X_add_number;
constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
_("immediate out of range"));
rot /= 90;
if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC))
return;
if (inst.operands[2].isscalar)
{
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
first_error (_("invalid instruction shape"));
enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
N_KEY | N_F16 | N_F32).size;
@ -19705,9 +19749,19 @@ do_vcmla (void)
}
else
{
enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
enum neon_shape rs;
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
rs = neon_select_shape (NS_QQQI, NS_NULL);
else
rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
N_KEY | N_F16 | N_F32).size;
if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
&& (inst.operands[0].reg == inst.operands[1].reg
|| inst.operands[0].reg == inst.operands[2].reg))
as_tsktsk (BAD_MVE_SRCDEST);
neon_three_same (neon_quad (rs), 0, -1);
inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
inst.instruction |= 0xfc200800;
@ -19719,20 +19773,60 @@ do_vcmla (void)
static void
do_vcadd (void)
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
_(BAD_FPU));
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
&& (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
|| !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
constraint (inst.relocs[0].exp.X_op != O_constant,
_("expression too complex"));
unsigned rot = inst.relocs[0].exp.X_add_number;
constraint (rot != 90 && rot != 270, _("immediate out of range"));
enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
N_KEY | N_F16 | N_F32).size;
neon_three_same (neon_quad (rs), 0, -1);
inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
inst.instruction |= 0xfc800800;
inst.instruction |= (rot == 270) << 24;
inst.instruction |= (size == 32) << 20;
enum neon_shape rs;
struct neon_type_el et;
if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
{
rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
}
else
{
rs = neon_select_shape (NS_QQQI, NS_NULL);
et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
| N_I16 | N_I32);
if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
as_tsktsk (_("Warning: 32-bit element size and same first and third "
"operand makes instruction UNPREDICTABLE"));
}
if (et.type == NT_invtype)
return;
if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8
| NEON_CHECK_CC))
return;
if (et.type == NT_float)
{
neon_three_same (neon_quad (rs), 0, -1);
inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
inst.instruction |= 0xfc800800;
inst.instruction |= (rot == 270) << 24;
inst.instruction |= (et.size == 32) << 20;
}
else
{
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
inst.instruction = 0xfe000f00;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= neon_logbits (et.size) << 20;
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= (rot == 270) << 12;
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= LOW4 (inst.operands[2].reg);
inst.is_neon = 1;
}
}
/* Dot Product instructions encoding support. */
@ -22719,8 +22813,6 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_3
NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla),
NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_neon_ext_dotprod
@ -24087,6 +24179,10 @@ static const struct asm_opcode insns[] =
mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1
#undef THUMB_VARIANT
@ -24141,6 +24237,13 @@ static const struct asm_opcode insns[] =
mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v8_3
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v6t2_v8m
MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT

5
gas/testsuite/gas/arm/mve-vcadd-bad-1.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VCADD instructions
#as: -march=armv8.1-m.main+mve
#error_output: mve-vcadd-bad-1.l
.*: +file format .*arm.*

17
gas/testsuite/gas/arm/mve-vcadd-bad-1.l Normal file
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@ -0,0 +1,17 @@
[^:]*: Assembler messages:
[^:]*:10: Error: selected FPU does not support instruction -- `vcadd.f16 q0,q1,q2,#90'
[^:]*:11: Error: bad type in SIMD instruction -- `vcadd.64 q0,q1,q2,#90'
[^:]*:12: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#180'
[^:]*:13: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#0'
[^:]*:14: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
[^:]*:18: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
[^:]*:20: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.i16 q0,q1,q2,#90'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcadd.i16 q0,q1,q2,#90'

23
gas/testsuite/gas/arm/mve-vcadd-bad-1.s Normal file
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@ -0,0 +1,23 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcadd.i16 q0, q1, q2, #90
.endr
.endm
.syntax unified
.thumb
vcadd.f16 q0, q1, q2, #90
vcadd.64 q0, q1, q2, #90
vcadd.i32 q0, q1, q2, #180
vcadd.i32 q0, q1, q2, #0
vcadd.i32 q0, q1, q0, #90
cond
it eq
vcaddeq.i16 q0, q1, q2, #90
vcaddeq.i16 q0, q1, q2, #90
vpst
vcaddeq.i16 q0, q1, q2, #90
vcaddt.i16 q0, q1, q2, #90
vpst
vcadd.i16 q0, q1, q2, #90

5
gas/testsuite/gas/arm/mve-vcadd-bad-2.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE FP VCADD instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vcadd-bad-2.l
.*: +file format .*arm.*

17
gas/testsuite/gas/arm/mve-vcadd-bad-2.l Normal file
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@ -0,0 +1,17 @@
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vcadd.f64 q0,q1,q2,#90'
[^:]*:11: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#180'
[^:]*:12: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#0'
[^:]*:13: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
[^:]*:17: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
[^:]*:19: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.f16 q0,q1,q2,#90'
[^:]*:22: Error: instruction missing MVE vector predication code -- `vcadd.f16 q0,q1,q2,#90'

22
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@ -0,0 +1,22 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcadd.f32 q0, q1, q2, #90
.endr
.endm
.syntax unified
.thumb
vcadd.f64 q0, q1, q2, #90
vcadd.f32 q0, q1, q2, #180
vcadd.f32 q0, q1, q2, #0
vcadd.f32 q0, q1, q0, #90
cond
it eq
vcaddeq.f16 q0, q1, q2, #90
vcaddeq.f16 q0, q1, q2, #90
vpst
vcaddeq.f16 q0, q1, q2, #90
vcaddt.f16 q0, q1, q2, #90
vpst
vcadd.f16 q0, q1, q2, #90

5
gas/testsuite/gas/arm/mve-vcmla-bad-1.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VCMLA instructions
#as: -march=armv8.1-m.main+mve
#error_output: mve-vcmla-bad-1.l
.*: +file format .*arm.*

3
gas/testsuite/gas/arm/mve-vcmla-bad-1.l Normal file
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@ -0,0 +1,3 @@
[^:]*: Assembler messages:
[^:]*:3: Error: selected FPU does not support instruction -- `vcmla.f16 q0,q1,q2,#0'
[^:]*:4: Error: selected FPU does not support instruction -- `vcmla.f32 q0,q1,q2,#0'

4
gas/testsuite/gas/arm/mve-vcmla-bad-1.s Normal file
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@ -0,0 +1,4 @@
.syntax unified
.thumb
vcmla.f16 q0, q1, q2, #0
vcmla.f32 q0, q1, q2, #0

5
gas/testsuite/gas/arm/mve-vcmla-bad-2.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE FP VCMLA instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vcmla-bad-2.l
.*: +file format .*arm.*

17
gas/testsuite/gas/arm/mve-vcmla-bad-2.l Normal file
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@ -0,0 +1,17 @@
[^:]*: Assembler messages:
[^:]*:10: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20'
[^:]*:11: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:13: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0'
[^:]*:14: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0'
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:18: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:20: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmlat.f16 q0,q1,q2,#0'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmla.f16 q0,q1,q2,#0'

23
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@ -0,0 +1,23 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcmla.f32 q0, q1, q2, #0
.endr
.endm
.syntax unified
.thumb
vcmla.f16 q0, q1, q2, #20
vcmla.f32 q0, q0, q1, #0
vcmla.f32 q0, q1, q0, #0
vcmla.f64 q0, q1, q2, #0
vcmla.i16 q0, q1, q2, #0
cond
it eq
vcmlaeq.f16 q0, q1, q2, #0
vcmlaeq.f16 q0, q1, q2, #0
vpst
vcmlaeq.f16 q0, q1, q2, #0
vcmlat.f16 q0, q1, q2, #0
vpst
vcmla.f16 q0, q1, q2, #0

5
gas/testsuite/gas/arm/mve-vcmul-bad-1.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VCMUL instructions
#as: -march=armv8.1-m.main+mve
#error_output: mve-vcmul-bad-1.l
.*: +file format .*arm.*

4
gas/testsuite/gas/arm/mve-vcmul-bad-1.l Normal file
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@ -0,0 +1,4 @@
[^:]*: Assembler messages:
[^:]*:3: Error: selected processor does not support `vcmul.f16 q0,q1,q2,#0' in Thumb mode
[^:]*:4: Error: selected processor does not support `vcmul.f32 q0,q1,q2,#0' in Thumb mode
[^:]*:5: Error: selected processor does not support `vcmul.i16 q0,q1,q2,#0' in Thumb mode

5
gas/testsuite/gas/arm/mve-vcmul-bad-1.s Normal file
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@ -0,0 +1,5 @@
.syntax unified
.thumb
vcmul.f16 q0, q1, q2, #0
vcmul.f32 q0, q1, q2, #0
vcmul.i16 q0, q1, q2, #0

5
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@ -0,0 +1,5 @@
#name: bad MVE FP VCMUL instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vcmul-bad-2.l
.*: +file format .*arm.*

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gas/testsuite/gas/arm/mve-vcmul-bad-2.l Normal file
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[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vcmul.i16 q0,q1,q2,#0'
[^:]*:11: Error: bad type in SIMD instruction -- `vcmul.f64 q0,q1,q2,#0'
[^:]*:12: Error: immediate out of range -- `vcmul.f32 q0,q1,q2,#20'
[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:14: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:17: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
[^:]*:18: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
[^:]*:20: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmult.f32 q0,q1,q2,#0'
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmul.f32 q0,q1,q2,#0'

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gas/testsuite/gas/arm/mve-vcmul-bad-2.s Normal file
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.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcmul.f32 q0, q1, q2, #0
.endr
.endm
.syntax unified
.thumb
vcmul.i16 q0, q1, q2, #0
vcmul.f64 q0, q1, q2, #0
vcmul.f32 q0, q1, q2, #20
vcmul.f32 q0, q1, q0, #0
vcmul.f32 q0, q0, q1, #0
cond
it eq
vcmuleq.f32 q0, q1, q2, #0
vcmuleq.f32 q0, q1, q2, #0
vpst
vcmuleq.f32 q0, q1, q2, #0
vcmult.f32 q0, q1, q2, #0
vpst
vcmul.f32 q0, q1, q2, #0