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sim: reg: constify store helper

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These functions only read from memory, so mark the pointer as const.
This commit is contained in:
Mike Frysinger
2022-10-26 23:01:21 +05:45
parent ed60d3edd5
commit 5bab16fdf1
38 changed files with 48 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/sim/sim.h
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@ -203,7 +203,8 @@ int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length);
Return a LENGTH of 0 to indicate the register was not updated Return a LENGTH of 0 to indicate the register was not updated
but no error has occurred. */ but no error has occurred. */
int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length); int sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf,
int length);
/* Print whatever statistics the simulator has collected. /* Print whatever statistics the simulator has collected.

2
sim/aarch64/interp.c
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@ -257,7 +257,7 @@ aarch64_reg_get (SIM_CPU *cpu, int regno, unsigned char *buf, int length)
} }
static int static int
aarch64_reg_set (SIM_CPU *cpu, int regno, unsigned char *buf, int length) aarch64_reg_set (SIM_CPU *cpu, int regno, const unsigned char *buf, int length)
{ {
size_t size; size_t size;
bfd_vma val; bfd_vma val;

2
sim/arm/wrapper.c
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@ -429,7 +429,7 @@ tomem (struct ARMul_State *state,
} }
static int static int
arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
init (); init ();

2
sim/avr/interp.c
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@ -1600,7 +1600,7 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size)
} }
static int static int
avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) avr_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
if (rn < 32 && length == 1) if (rn < 32 && length == 1)
{ {

2
sim/bfin/machs.c
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@ -1881,7 +1881,7 @@ bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
} }
static int static int
bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len) bfin_reg_store (SIM_CPU *cpu, int rn, const unsigned char *buf, int len)
{ {
bu32 value, *reg; bu32 value, *reg;

2
sim/bpf/bpf.c
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@ -61,7 +61,7 @@ bpfbf_fetch_register (SIM_CPU *current_cpu,
int int
bpfbf_store_register (SIM_CPU *current_cpu, bpfbf_store_register (SIM_CPU *current_cpu,
int rn, int rn,
unsigned char *buf, const unsigned char *buf,
int len) int len)
{ {
if (rn == 11) if (rn == 11)

2
sim/common/sim-cpu.h
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@ -31,7 +31,7 @@ typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
/* Types for register access functions. /* Types for register access functions.
These routines implement the sim_{fetch,store}_register interface. */ These routines implement the sim_{fetch,store}_register interface. */
typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int); typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int); typedef int (CPUREG_STORE_FN) (sim_cpu *, int, const unsigned char *, int);
/* Types for PC access functions. /* Types for PC access functions.
Some simulators require a functional interface to access the program Some simulators require a functional interface to access the program

2
sim/common/sim-reg.c
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@ -45,7 +45,7 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
cpus. */ cpus. */
int int
sim_store_register (SIM_DESC sd, int rn, unsigned char *buf, int length) sim_store_register (SIM_DESC sd, int rn, const unsigned char *buf, int length)
{ {
SIM_CPU *cpu = STATE_CPU (sd, 0); SIM_CPU *cpu = STATE_CPU (sd, 0);

4
sim/cr16/interp.c
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@ -386,7 +386,7 @@ free_state (SIM_DESC sd)
} }
static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int cr16_reg_store (SIM_CPU *, int, unsigned char *, int); static int cr16_reg_store (SIM_CPU *, int, const unsigned char *, int);
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
@ -769,7 +769,7 @@ cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
} }
static int static int
cr16_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) cr16_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
SIM_DESC sd = CPU_STATE (cpu); SIM_DESC sd = CPU_STATE (cpu);
int size; int size;

2
sim/cris/cris-tmpl.c
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@ -90,7 +90,7 @@ MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
int int
MY (f_store_register) (SIM_CPU *current_cpu, int rn, MY (f_store_register) (SIM_CPU *current_cpu, int rn,
unsigned char *buf, int len ATTRIBUTE_UNUSED) const unsigned char *buf, int len ATTRIBUTE_UNUSED)
{ {
XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf)); XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
return -1; return -1;

2
sim/cris/sim-if.c
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@ -933,7 +933,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
CPU_CRIS_MISC_PROFILE (cpu)->flags = STATE_TRACE_FLAGS (sd)[0]; CPU_CRIS_MISC_PROFILE (cpu)->flags = STATE_TRACE_FLAGS (sd)[0];
/* Set SP to the stack we allocated above. */ /* Set SP to the stack we allocated above. */
(* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (unsigned char *) sp_init, 4); (* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (const unsigned char *) sp_init, 4);
/* Set the simulator environment data. */ /* Set the simulator environment data. */
cpu->highest_mmapped_page = NULL; cpu->highest_mmapped_page = NULL;

4
sim/d10v/interp.c
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@ -744,7 +744,7 @@ free_state (SIM_DESC sd)
} }
static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int d10v_reg_store (SIM_CPU *, int, unsigned char *, int); static int d10v_reg_store (SIM_CPU *, int, const unsigned char *, int);
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *cb, sim_open (SIM_OPEN_KIND kind, host_callback *cb,
@ -1293,7 +1293,7 @@ d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
} }
static int static int
d10v_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) d10v_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
SIM_DESC sd = CPU_STATE (cpu); SIM_DESC sd = CPU_STATE (cpu);
int size; int size;

2
sim/erc32/interf.c
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@ -310,7 +310,7 @@ sim_create_inferior(SIM_DESC sd, bfd *abfd, char * const *argv,
} }
int int
sim_store_register(SIM_DESC sd, int regno, unsigned char *value, int length) sim_store_register(SIM_DESC sd, int regno, const unsigned char *value, int length)
{ {
int regval; int regval;

2
sim/frv/frv.c
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@ -89,7 +89,7 @@ frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
/* The contents of BUF are in target byte order. */ /* The contents of BUF are in target byte order. */
int int
frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) frvbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len)
{ {
if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM) if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM)
{ {

2
sim/ft32/interp.c
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@ -745,7 +745,7 @@ ft32_lookup_register (SIM_CPU *cpu, int nr)
static int static int
ft32_reg_store (SIM_CPU *cpu, ft32_reg_store (SIM_CPU *cpu,
int rn, int rn,
unsigned char *memory, const unsigned char *memory,
int length) int length)
{ {
if (0 <= rn && rn <= 32) if (0 <= rn && rn <= 32)

2
sim/h8300/compile.c
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@ -4476,7 +4476,7 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size)
} }
static int static int
h8300_reg_store (SIM_CPU *cpu, int rn, unsigned char *value, int length) h8300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *value, int length)
{ {
int longval; int longval;
int shortval; int shortval;

2
sim/iq2000/iq2000.c
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@ -227,7 +227,7 @@ iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
} }
int int
iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len) iq2000bf_store_register (SIM_CPU *cpu, int nr, const unsigned char *buf, int len)
{ {
if (nr >= GPR0_REGNUM if (nr >= GPR0_REGNUM
&& nr < (GPR0_REGNUM + NR_GPR) && nr < (GPR0_REGNUM + NR_GPR)

2
sim/lm32/lm32.c
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@ -52,7 +52,7 @@ lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
/* The contents of BUF are in target byte order. */ /* The contents of BUF are in target byte order. */
int int
lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf, lm32bf_store_register (SIM_CPU * current_cpu, int rn, const unsigned char *buf,
int len) int len)
{ {
if (rn < 32) if (rn < 32)

2
sim/m32c/gdb-if.c
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@ -403,7 +403,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
} }
int int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length)
{ {
size_t size; size_t size;

2
sim/m32r/m32r.c
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@ -98,7 +98,7 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
/* The contents of BUF are in target byte order. */ /* The contents of BUF are in target byte order. */
int int
m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) m32rbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len)
{ {
int size = m32rbf_register_size (rn); int size = m32rbf_register_size (rn);
if (len != size) if (len != size)

2
sim/m32r/m32r2.c
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@ -38,7 +38,7 @@ m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
/* The contents of BUF are in target byte order. */ /* The contents of BUF are in target byte order. */
int int
m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) m32r2f_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len)
{ {
return m32rbf_store_register (current_cpu, rn, buf, len); return m32rbf_store_register (current_cpu, rn, buf, len);
} }

2
sim/m32r/m32rx.c
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@ -38,7 +38,7 @@ m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
/* The contents of BUF are in target byte order. */ /* The contents of BUF are in target byte order. */
int int
m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) m32rxf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len)
{ {
return m32rbf_store_register (current_cpu, rn, buf, len); return m32rbf_store_register (current_cpu, rn, buf, len);
} }

4
sim/m68hc11/interp.c
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@ -392,7 +392,7 @@ m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
} }
static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int m68hc11_reg_store (SIM_CPU *, int, unsigned char *, int); static int m68hc11_reg_store (SIM_CPU *, int, const unsigned char *, int);
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback, sim_open (SIM_OPEN_KIND kind, host_callback *callback,
@ -595,7 +595,7 @@ m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
} }
static int static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) m68hc11_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
uint16_t val; uint16_t val;

2
sim/mcore/interp.c
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@ -1242,7 +1242,7 @@ sim_engine_run (SIM_DESC sd,
} }
static int static int
mcore_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) mcore_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
if (rn < NUM_MCORE_REGS && rn >= 0) if (rn < NUM_MCORE_REGS && rn >= 0)
{ {

2
sim/microblaze/interp.c
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@ -321,7 +321,7 @@ sim_engine_run (SIM_DESC sd,
} }
static int static int
microblaze_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) microblaze_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0) if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
{ {

4
sim/mips/interp.c
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@ -337,7 +337,7 @@ mips_pc_set (sim_cpu *cpu, sim_cia pc)
} }
static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int mips_reg_store (SIM_CPU *, int, unsigned char *, int); static int mips_reg_store (SIM_CPU *, int, const unsigned char *, int);
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *cb, sim_open (SIM_OPEN_KIND kind, host_callback *cb,
@ -846,7 +846,7 @@ mips_sim_close (SIM_DESC sd, int quitting)
} }
static int static int
mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) mips_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
/* NOTE: gdb (the client) stores registers in target byte order /* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */ while the simulator uses host byte order */

6
sim/mn10300/interp.c
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@ -80,7 +80,7 @@ mn10300_pc_set (sim_cpu *cpu, sim_cia pc)
} }
static int mn10300_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int mn10300_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int mn10300_reg_store (SIM_CPU *, int, unsigned char *, int); static int mn10300_reg_store (SIM_CPU *, int, const unsigned char *, int);
/* These default values correspond to expected usage for the chip. */ /* These default values correspond to expected usage for the chip. */
@ -344,9 +344,9 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
} }
static int static int
mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) mn10300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
uint8_t *a = memory; const uint8_t *a = memory;
State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0]; State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0];
return length; return length;
} }

2
sim/moxie/interp.c
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@ -1132,7 +1132,7 @@ sim_engine_run (SIM_DESC sd,
} }
static int static int
moxie_reg_store (SIM_CPU *scpu, int rn, unsigned char *memory, int length) moxie_reg_store (SIM_CPU *scpu, int rn, const unsigned char *memory, int length)
{ {
if (rn < NUM_MOXIE_REGS && rn >= 0) if (rn < NUM_MOXIE_REGS && rn >= 0)
{ {

2
sim/msp430/msp430-sim.c
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@ -74,7 +74,7 @@ msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
} }
static int static int
msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len) msp430_reg_store (SIM_CPU *cpu, int regno, const unsigned char *buf, int len)
{ {
if (0 <= regno && regno < 16) if (0 <= regno && regno < 16)
{ {

4
sim/or1k/or1k-sim.h
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@ -70,8 +70,8 @@ void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val);
int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf, int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
int len); int len);
int or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf, int or1k32bf_store_register (sim_cpu *current_cpu, int rn,
int len); const unsigned char *buf, int len);
int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc, int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc,
int unit_num, int referenced); int unit_num, int referenced);
int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc, int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc,

2
sim/or1k/or1k.c
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@ -55,7 +55,7 @@ or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf,
} }
int int
or1k32bf_store_register (sim_cpu *current_cpu, int rn, unsigned char *buf, or1k32bf_store_register (sim_cpu *current_cpu, int rn, const unsigned char *buf,
int len) int len)
{ {
if (rn < 32) if (rn < 32)

3
sim/ppc/gdb-sim.c
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@ -1284,7 +1284,8 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
int int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf,
int length)
{ {
const char *regname = regnum2name (regno); const char *regname = regnum2name (regno);

2
sim/pru/interp.c
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@ -650,7 +650,7 @@ pru_pc_set (sim_cpu *cpu, sim_cia pc)
/* Implement callback for standard CPU_REG_STORE routine. */ /* Implement callback for standard CPU_REG_STORE routine. */
static int static int
pru_store_register (SIM_CPU *cpu, int rn, unsigned char *memory, int length) pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
if (rn < NUM_REGS && rn >= 0) if (rn < NUM_REGS && rn >= 0)
{ {

2
sim/riscv/sim-main.c
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@ -1054,7 +1054,7 @@ reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, int len)
} }
static int static int
reg_store (sim_cpu *cpu, int rn, unsigned char *buf, int len) reg_store (sim_cpu *cpu, int rn, const unsigned char *buf, int len)
{ {
if (len <= 0 || len > sizeof (unsigned_word)) if (len <= 0 || len > sizeof (unsigned_word))
return -1; return -1;

2
sim/rl78/gdb-if.c
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@ -356,7 +356,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
LENGTH must match the sim's internal notion of the register size. */ LENGTH must match the sim's internal notion of the register size. */
int int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length)
{ {
size_t size; size_t size;
SI val; SI val;

2
sim/rx/gdb-if.c
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@ -532,7 +532,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
} }
int int
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length) sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length)
{ {
size_t size; size_t size;
DI val; DI val;

2
sim/sh/interp.c
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@ -1913,7 +1913,7 @@ enum {
}; };
static int static int
sh_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) sh_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
unsigned val; unsigned val;

4
sim/v850/interp.c
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@ -185,7 +185,7 @@ v850_pc_set (sim_cpu *cpu, sim_cia pc)
} }
static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
static int v850_reg_store (SIM_CPU *, int, unsigned char *, int); static int v850_reg_store (SIM_CPU *, int, const unsigned char *, int);
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, sim_open (SIM_OPEN_KIND kind,
@ -320,7 +320,7 @@ v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
} }
static int static int
v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) v850_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length)
{ {
State.regs[rn] = T2H_4 (*(uint32_t *) memory); State.regs[rn] = T2H_4 (*(uint32_t *) memory);
return length; return length;