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bfd/

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2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* cpu-ia64-opc.c (ins_immu5b): New.
	(ext_immu5b): Likewise.
	(elf64_ia64_operands): Add IMMU5b.

gas/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.

gas/testsuite/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/ia64/opc-i.s: Add tests for tf.
	* gas/ia64/pseudo.s: Likewise.
	* gas/ia64/opc-i.d: Updated.
	* gas/ia64/pseudo.d: Likewise.

include/opcode/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.

opcodes/

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.
This commit is contained in:
H.J. Lu
2006-02-23 21:36:18 +00:00
parent 921286914f
commit 59cf82fe74
15 changed files with 5236 additions and 4934 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
bfd/ChangeLog
View File

@ -1,3 +1,9 @@
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* cpu-ia64-opc.c (ins_immu5b): New.
(ext_immu5b): Likewise.
(elf64_ia64_operands): Add IMMU5b.
2006-02-21 Alan Modra <amodra@bigpond.net.au>
PR ld/2218

27
bfd/cpu-ia64-opc.c
View File

@ -1,4 +1,4 @@
/* Copyright 1998, 1999, 2000, 2001, 2002, 2003
/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
@ -113,6 +113,29 @@ ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
return 0;
}
static const char*
ins_immu5b (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code)
{
if (value < 32 || value > 63)
return "value must be between 32 and 63";
return ins_immu (self, value - 32, code);
}
static const char*
ext_immu5b (const struct ia64_operand *self, ia64_insn code,
ia64_insn *valuep)
{
const char *result;
result = ext_immu (self, code, valuep);
if (result)
return result;
*valuep = *valuep + 32;
return 0;
}
static const char*
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
@ -506,6 +529,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
"a 1-bit integer (-1, 0)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
"a 2-bit unsigned (0-3)" },
{ ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */
"a 5-bit unsigned (32 + (0-31))" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */

4
gas/ChangeLog
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@ -1,3 +1,7 @@
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c: Update copyright years.

11
gas/config/tc-ia64.c
View File

@ -5914,6 +5914,17 @@ operand_match (idesc, index, e)
return OPERAND_MATCH;
break;
case IA64_OPND_IMMU5b:
if (e->X_op == O_constant)
{
val = e->X_add_number;
if (val >= 32 && val <= 63)
return OPERAND_MATCH;
else
return OPERAND_OUT_OF_RANGE;
}
break;
case IA64_OPND_CCNT5:
case IA64_OPND_CNT5:
case IA64_OPND_CNT6:

7
gas/testsuite/ChangeLog
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@ -1,3 +1,10 @@
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/opc-i.s: Add tests for tf.
* gas/ia64/pseudo.s: Likewise.
* gas/ia64/opc-i.d: Updated.
* gas/ia64/pseudo.d: Likewise.
2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-raw-err.s: Add check for vmsw.0.

54
gas/testsuite/gas/ia64/opc-i.d
View File

@ -259,6 +259,54 @@ Disassembly of section \.text:
ab0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
ab6: 01 00 00 03 80 03 \(p07\) hint\.i 0x0
abc: 00 00 06 00 \(p07\) hint\.i 0x0
ac0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
ac6: 00 00 00 02 80 e3 nop\.f 0x0
acc: ff ff 07 08 \(p07\) hint\.i 0x1fffff;;
ac0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
ac6: f1 ff ff 03 04 40 \(p07\) hint\.i 0x1fffff
acc: f0 04 0c 50 tf\.z p2,p3=39
ad0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
ad6: 20 7c 02 06 28 40 tf\.z\.unc p2,p3=39
adc: f0 04 0c 58 tf\.z\.and p2,p3=39
ae0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
ae6: 20 78 02 86 28 40 tf\.z\.or p2,p3=39
aec: f0 04 0c 59 tf\.z\.or\.andcm p2,p3=39
af0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
af6: 30 7c 02 84 28 60 tf\.nz\.or p3,p2=39
afc: f8 04 08 58 tf\.nz\.and p3,p2=39
b00: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b06: 30 7c 02 84 2c 60 tf\.nz\.or\.andcm p3,p2=39
b0c: f0 04 08 50 tf\.z p3,p2=39
b10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b16: 30 7c 02 04 28 40 tf\.z\.unc p3,p2=39
b1c: f8 04 0c 58 tf\.nz\.and p2,p3=39
b20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b26: 20 7c 02 86 28 40 tf\.nz\.or p2,p3=39
b2c: f8 04 0c 59 tf\.nz\.or\.andcm p2,p3=39
b30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b36: 30 78 02 84 28 60 tf\.z\.or p3,p2=39
b3c: f0 04 08 58 tf\.z\.and p3,p2=39
b40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b46: 30 78 02 84 ac 43 tf\.z\.or\.andcm p3,p2=39
b4c: f0 04 0c 50 \(p07\) tf\.z p2,p3=39
b50: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
b56: 21 7c 02 06 a8 43 \(p07\) tf\.z\.unc p2,p3=39
b5c: f0 04 0c 58 \(p07\) tf\.z\.and p2,p3=39
b60: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
b66: 21 78 02 86 a8 43 \(p07\) tf\.z\.or p2,p3=39
b6c: f0 04 0c 59 \(p07\) tf\.z\.or\.andcm p2,p3=39
b70: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
b76: 31 7c 02 84 a8 63 \(p07\) tf\.nz\.or p3,p2=39
b7c: f8 04 08 58 \(p07\) tf\.nz\.and p3,p2=39
b80: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
b86: 31 7c 02 84 ac 63 \(p07\) tf\.nz\.or\.andcm p3,p2=39
b8c: f0 04 08 50 \(p07\) tf\.z p3,p2=39
b90: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
b96: 31 7c 02 04 a8 43 \(p07\) tf\.z\.unc p3,p2=39
b9c: f8 04 0c 58 \(p07\) tf\.nz\.and p2,p3=39
ba0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
ba6: 21 7c 02 86 a8 43 \(p07\) tf\.nz\.or p2,p3=39
bac: f8 04 0c 59 \(p07\) tf\.nz\.or\.andcm p2,p3=39
bb0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
bb6: 31 78 02 84 a8 63 \(p07\) tf\.z\.or p3,p2=39
bbc: f0 04 08 58 \(p07\) tf\.z\.and p3,p2=39
bc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
bc6: 00 00 00 02 80 63 nop\.f 0x0
bcc: f0 04 08 59 \(p07\) tf\.z\.or\.andcm p3,p2=39;;

36
gas/testsuite/gas/ia64/opc-i.s
View File

@ -220,3 +220,39 @@ _start:
(p7) hint.i 0
(p7) hint.i @pause
(p7) hint.i 0x1fffff
# instructions added by SDM2.2:
tf.z p2, p3 = 39
tf.z.unc p2, p3 = 39
tf.z.and p2, p3 = 39
tf.z.or p2, p3 = 39
tf.z.or.andcm p2, p3 = 39
tf.z.orcm p2, p3 = 39
tf.z.andcm p2, p3 = 39
tf.z.and.orcm p2, p3 = 39
tf.nz p2, p3 = 39
tf.nz.unc p2, p3 = 39
tf.nz.and p2, p3 = 39
tf.nz.or p2, p3 = 39
tf.nz.or.andcm p2, p3 = 39
tf.nz.orcm p2, p3 = 39
tf.nz.andcm p2, p3 = 39
tf.nz.and.orcm p2, p3 = 39
(p7) tf.z p2, p3 = 39
(p7) tf.z.unc p2, p3 = 39
(p7) tf.z.and p2, p3 = 39
(p7) tf.z.or p2, p3 = 39
(p7) tf.z.or.andcm p2, p3 = 39
(p7) tf.z.orcm p2, p3 = 39
(p7) tf.z.andcm p2, p3 = 39
(p7) tf.z.and.orcm p2, p3 = 39
(p7) tf.nz p2, p3 = 39
(p7) tf.nz.unc p2, p3 = 39
(p7) tf.nz.and p2, p3 = 39
(p7) tf.nz.or p2, p3 = 39
(p7) tf.nz.or.andcm p2, p3 = 39
(p7) tf.nz.orcm p2, p3 = 39
(p7) tf.nz.andcm p2, p3 = 39
(p7) tf.nz.and.orcm p2, p3 = 39

2
gas/testsuite/gas/ia64/pseudo.d
View File

@ -25,3 +25,5 @@ Disassembly of section \.text:
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+st16 \[r0\]=r0,ar\.csd
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tbit\.z p0,p12=r0,0
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tnat\.z p0,p13=r0(;;)?
#...
[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tf\.z p3,p2=33(;;)?

4
gas/testsuite/gas/ia64/pseudo.s
View File

@ -13,3 +13,7 @@ _start:
st16 [r0] = r0
tbit.nz p12 = r0, 0
tnat.nz p13 = r0
# instructions added by SDM2.2:
tf.nz p2, p3 = 33

4
include/opcode/ChangeLog
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@ -1,3 +1,7 @@
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
2006-01-31 Paul Brook <paul@codesourcery.com>
Richard Earnshaw <rearnsha@arm.com>

4
include/opcode/ia64.h
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@ -1,5 +1,6 @@
/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
#ifndef opcode_ia64_h
@ -102,6 +103,7 @@ enum ia64_opnd
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
IA64_OPND_SOF, /* 8-bit stack frame size */

13
opcodes/ChangeLog
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@ -1,3 +1,16 @@
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64-opc-i.c (bXc): New.
(mXc): Likewise.
(OpX2TaTbYaXcC): Likewise.
(TF). Likewise.
(TFCM). Likewise.
(ia64_opcodes_i): Add instructions for tf.
* ia64-opc.h (IMMU5b): New.
* ia64-asmtab.c: Regenerated.
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64-gen.c: Update copyright years.

9962
opcodes/ia64-asmtab.c
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File diff suppressed because it is too large Load Diff

30
opcodes/ia64-opc-i.c
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@ -1,5 +1,6 @@
/* ia64-opc-i.c -- IA-64 `I' opcode table.
Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc.
Copyright 1998, 1999, 2000, 2002, 2005, 2006
Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
@ -36,6 +37,7 @@
#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
@ -58,6 +60,7 @@
#define mWh bWh (-1)
#define mX bX (-1)
#define mXb bXb (-1)
#define mXc bXc (-1)
#define mX2 bX2 (-1)
#define mX2a bX2a (-1)
#define mX2b bX2b (-1)
@ -83,6 +86,9 @@
#define OpX2TaTbYaC(a,b,c,d,e,f) \
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
(mOp | mX2 | mTa | mTb | mYa | mC)
#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
(mOp | mX2 | mTa | mTb | mYa | mXc | mC)
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
@ -164,6 +170,28 @@ struct ia64_opcode ia64_opcodes_i[] =
{"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
{"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
{"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
#define TF(a,b,c) \
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
#define TFCM(a,b,c) \
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
{"tf.z", TF (0, 0, 0)},
{"tf.nz", TFCM (0, 0, 0)},
{"tf.z.unc", TF (0, 0, 1)},
{"tf.nz.unc", TFCM (0, 0, 1)},
{"tf.z.and", TF (0, 1, 0)},
{"tf.nz.andcm", TFCM (0, 1, 0)},
{"tf.nz.and", TF (0, 1, 1)},
{"tf.z.andcm", TFCM (0, 1, 1)},
{"tf.z.or", TF (1, 0, 0)},
{"tf.nz.orcm", TFCM (1, 0, 0)},
{"tf.nz.or", TF (1, 0, 1)},
{"tf.z.orcm", TFCM (1, 0, 1)},
{"tf.z.or.andcm", TF (1, 1, 0)},
{"tf.nz.and.orcm", TFCM (1, 1, 0)},
{"tf.nz.or.andcm", TF (1, 1, 1)},
{"tf.z.and.orcm", TFCM (1, 1, 1)},
#undef TF
#undef TFCM
#define TBIT(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
#define TBITCM(a,b,c,d) \

4
opcodes/ia64-opc.h
View File

@ -1,5 +1,6 @@
/* ia64-opc.h -- IA-64 opcode table.
Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
Copyright 1998, 1999, 2000, 2002, 2005, 2006
Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
@ -112,6 +113,7 @@
#define IMMU24 IA64_OPND_IMMU24
#define IMMU62 IA64_OPND_IMMU62
#define IMMU64 IA64_OPND_IMMU64
#define IMMU5b IA64_OPND_IMMU5b
#define IMMU7a IA64_OPND_IMMU7a
#define IMMU7b IA64_OPND_IMMU7b
#define IMMU9 IA64_OPND_IMMU9