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opcodes: blackfin: fix decoding of LSHIFT insns

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The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT.  So be specific when disassembling.

As fall out of this change, we need to update some assembler tests.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2010-09-22 20:37:25 +00:00
parent 528c6277f7
commit 59a82d2333
8 changed files with 24 additions and 14 deletions
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4
opcodes/bfin-dis.c
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@ -4054,7 +4054,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
else if (sop == 2 && sopcde == 2)
{
OUTS (outf, dregs (dst0));
OUTS (outf, " = SHIFT ");
OUTS (outf, " = LSHIFT ");
OUTS (outf, dregs (src1));
OUTS (outf, " BY ");
OUTS (outf, dregs_lo (src0));
@ -4070,7 +4070,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
else if (sop == 2 && sopcde == 1)
{
OUTS (outf, dregs (dst0));
OUTS (outf, " = SHIFT ");
OUTS (outf, " = LSHIFT ");
OUTS (outf, dregs (src1));
OUTS (outf, " BY ");
OUTS (outf, dregs_lo (src0));