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2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>

Browse Source 
* config/tc-arm.c: Change condition code insertion for
	lds[hb] instructions from after the 2nd character to after the 3rd.
	(tCM): Remove macro.
	(TxCM): Likewise.
	(TxCM_): Likewise.
	(TCM): Likewise.

2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/ldgesb-bad.d: New file.
	* gas/arm/ldgesb-bad.l: Likewise.
	* gas/arm/ldgesb-bad.s: Likewise.
	* gas/arm/ldgesh-bad.d: Likewise.
	* gas/arm/ldgesh-bad.l: Likewise.
	* gas/arm/ldgesh-bad.s: Likewise.
	* gas/arm/ldsgeb.d: Likewise.
	* gas/arm/ldsgeb.s: Likewise.
	* gas/arm/ldsgeb.l: Likewise.
	* gas/arm/ldsgeh.d: Likewise.
	* gas/arm/ldsgeh.s: Likewise.
	* gas/arm/ldsgeh.l: Likewise.
This commit is contained in:
Richard Earnshaw
2012-10-11 15:26:18 +00:00
parent 7c1cef979f
commit 56c0a61f59
15 changed files with 74 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
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@ -1,3 +1,12 @@
2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c: Change condition code insertion for
lds[hb] instructions from after the 2nd character to after the 3rd.
(tCM): Remove macro.
(TxCM): Likewise.
(TxCM_): Likewise.
(TCM): Likewise.
2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS. * config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS.

37
gas/config/tc-arm.c
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@ -17778,38 +17778,6 @@ static struct asm_barrier_opt barrier_opt_names[] =
#define tC3w(mnem, aop, top, nops, ops, ae, te) \ #define tC3w(mnem, aop, top, nops, ops, ae, te) \
TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
appear in the condition table. */
#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
{ m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
#define TxCM(m1, m2, op, top, nops, ops, ae, te) \
TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
#define TCM(m1,m2, aop, top, nops, ops, ae, te) \
TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
#define tCM(m1,m2, aop, top, nops, ops, ae, te) \
TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
/* Mnemonic that cannot be conditionalized. The ARM condition-code /* Mnemonic that cannot be conditionalized. The ARM condition-code
field is still 0xE. Many of the Thumb variants can be executed field is still 0xE. Many of the Thumb variants can be executed
conditionally, so this is checked separately. */ conditionally, so this is checked separately. */
@ -18101,8 +18069,8 @@ static const struct asm_opcode insns[] =
tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
#undef ARM_VARIANT #undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v4t_5 #define ARM_VARIANT & arm_ext_v4t_5
@ -19781,7 +19749,6 @@ static const struct asm_opcode insns[] =
#undef ARM_VARIANT #undef ARM_VARIANT
#undef THUMB_VARIANT #undef THUMB_VARIANT
#undef TCE #undef TCE
#undef TCM
#undef TUE #undef TUE
#undef TUF #undef TUF
#undef TCC #undef TCC

15
gas/testsuite/ChangeLog
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@ -1,3 +1,18 @@
2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gas/arm/ldgesb-bad.d: New file.
* gas/arm/ldgesb-bad.l: Likewise.
* gas/arm/ldgesb-bad.s: Likewise.
* gas/arm/ldgesh-bad.d: Likewise.
* gas/arm/ldgesh-bad.l: Likewise.
* gas/arm/ldgesh-bad.s: Likewise.
* gas/arm/ldsgeb.d: Likewise.
* gas/arm/ldsgeb.s: Likewise.
* gas/arm/ldsgeb.l: Likewise.
* gas/arm/ldsgeh.d: Likewise.
* gas/arm/ldsgeh.s: Likewise.
* gas/arm/ldsgeh.l: Likewise.
2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* gas/i386/i386.exp: Run bdver3 test cases. * gas/i386/i386.exp: Run bdver3 test cases.

3
gas/testsuite/gas/arm/ldgesb-bad.d Normal file
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@ -0,0 +1,3 @@
# name: Reject ld<cc>sb instructions
# as: -march=armv7-a
# error-output: ldgesb-bad.l

3
gas/testsuite/gas/arm/ldgesb-bad.l Normal file
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@ -0,0 +1,3 @@
.*: Assembler messages:
.*Error: bad instruction `ldgesb r1,\[r11,#4\]'
.*Warning: section '.text' finished with an open IT block.

7
gas/testsuite/gas/arm/ldgesb-bad.s Normal file
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@ -0,0 +1,7 @@
.syntax unified
.arch armv7-a
.thumb
.global foo
foo:
it ge
ldgesb r1, [r11, #4]

3
gas/testsuite/gas/arm/ldgesh-bad.d Normal file
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@ -0,0 +1,3 @@
# name: Reject ld<cc>sh instructions
# as: -march=armv7-a
# error-output: ldgesh-bad.l

3
gas/testsuite/gas/arm/ldgesh-bad.l Normal file
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@ -0,0 +1,3 @@
.*: Assembler messages:
.*Error: bad instruction `ldgesh r1,\[r11,#4\]'
.*Warning: section '.text' finished with an open IT block.

7
gas/testsuite/gas/arm/ldgesh-bad.s Normal file
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@ -0,0 +1,7 @@
.syntax unified
.arch armv7-a
.thumb
.global foo
foo:
it ge
ldgesh r1, [r11, #4]

2
gas/testsuite/gas/arm/ldsgeb.d Normal file
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@ -0,0 +1,2 @@
# name: Accept lds<cc>sb mnemonics
# error-output: ldsgeb.l

2
gas/testsuite/gas/arm/ldsgeb.l Normal file
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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Warning: conditional infixes are deprecated in unified syntax

7
gas/testsuite/gas/arm/ldsgeb.s Normal file
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@ -0,0 +1,7 @@
.syntax unified
.arch armv7-a
.thumb
.global foo
foo:
it ge
ldsgeb r1, [r11, #4]

2
gas/testsuite/gas/arm/ldsgeh.d Normal file
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@ -0,0 +1,2 @@
# name: Accept lds<cc>sh mnemonics
# error-output: ldsgeh.l

2
gas/testsuite/gas/arm/ldsgeh.l Normal file
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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Warning: conditional infixes are deprecated in unified syntax

7
gas/testsuite/gas/arm/ldsgeh.s Normal file
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@ -0,0 +1,7 @@
.syntax unified
.arch armv7-a
.thumb
.global foo
foo:
it ge
ldsgeh r1, [r11, #4]