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aarch64: Update feature RAS system registers

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This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.

Please note that early Armv8-A architectures do not officially support RAS
extension.

Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.

The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.

RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.

For details see [0].

[0] https://developer.arm.com/docs/ddi0595/i/
This commit is contained in:
Przemyslaw Wirkus
2020-11-04 20:47:06 +00:00
parent 9c91c72591
commit 55cc012834
15 changed files with 102 additions and 143 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
gas/ChangeLog
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@ -1,3 +1,16 @@
2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/armv8-ras-1_1-invalid.d: New test.
* testsuite/gas/aarch64/armv8-ras-1_1-invalid.l: New test.
* testsuite/gas/aarch64/armv8-ras-1_1-invalid.s: New test.
* testsuite/gas/aarch64/armv8-ras-1_1.d: New test.
* testsuite/gas/aarch64/armv8-ras-1_1.s: New test.
* testsuite/gas/aarch64/illegal-ras-1.d: Remove.
* testsuite/gas/aarch64/illegal-ras-1.l: Remove.
* testsuite/gas/aarch64/illegal-ras-1.s: Remove.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Remove.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Remove.
2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs. * NEWS: Update docs.

3
gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.d Normal file
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@ -0,0 +1,3 @@
#name: Invalid RAS 1.1 System registers usage
#source: armv8-ras-1_1-invalid.s
#warning_output: armv8-ras-1_1-invalid.l

2
gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.l Normal file
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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1 -- `msr erxpfgf_el1,x0'

2
gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.s Normal file
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@ -0,0 +1,2 @@
/* Write to R/O RAS 1.1 system register. */
msr erxpfgf_el1, x0

26
gas/testsuite/gas/aarch64/armv8-ras-1_1.d Normal file
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@ -0,0 +1,26 @@
#name: RAS 1.1 System registers
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d5385540 mrs x0, erxmisc2_el1
.*: d5385560 mrs x0, erxmisc3_el1
.*: d53854c0 mrs x0, erxpfgcdn_el1
.*: d53854a0 mrs x0, erxpfgctl_el1
.*: d5185540 msr erxmisc2_el1, x0
.*: d5185560 msr erxmisc3_el1, x0
.*: d51854c0 msr erxpfgcdn_el1, x0
.*: d51854a0 msr erxpfgctl_el1, x0
.*: d5385480 mrs x0, erxpfgf_el1
.*: d5385540 mrs x0, erxmisc2_el1
.*: d5385560 mrs x0, erxmisc3_el1
.*: d53854c0 mrs x0, erxpfgcdn_el1
.*: d53854a0 mrs x0, erxpfgctl_el1
.*: d5185540 msr erxmisc2_el1, x0
.*: d5185560 msr erxmisc3_el1, x0
.*: d51854c0 msr erxpfgcdn_el1, x0
.*: d51854a0 msr erxpfgctl_el1, x0
.*: d5385480 mrs x0, erxpfgf_el1

39
gas/testsuite/gas/aarch64/armv8-ras-1_1.s Normal file
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@ -0,0 +1,39 @@
/* Armv8-A RAS 1.1 extension system registers.
Please note that early Armv8-a architectures do not officially support RAS
extension.
Certain use cases require developers to enable only more generic architecture
(e.g. -march=armv8-a) during system development. Users must use RAS extension
registers bearing in mind that system they use must support it. */
/* Arm8-A. */
.arch armv8-a
/* RAS 1.1 Read/Write registers. */
mrs x0, erxmisc2_el1
mrs x0, erxmisc3_el1
mrs x0, erxpfgcdn_el1
mrs x0, erxpfgctl_el1
msr erxmisc2_el1, x0
msr erxmisc3_el1, x0
msr erxpfgcdn_el1, x0
msr erxpfgctl_el1, x0
/* RAS 1.1 Read-only registers. */
mrs x0, erxpfgf_el1
/* Armv8-A + RAS. */
.arch armv8-a+ras
/* RAS 1.1 Read/Write registers. */
mrs x0, erxmisc2_el1
mrs x0, erxmisc3_el1
mrs x0, erxpfgcdn_el1
mrs x0, erxpfgctl_el1
msr erxmisc2_el1, x0
msr erxmisc3_el1, x0
msr erxpfgcdn_el1, x0
msr erxpfgctl_el1, x0
/* RAS 1.1 Read-only registers. */
mrs x0, erxpfgf_el1

4
gas/testsuite/gas/aarch64/illegal-ras-1.d
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@ -1,4 +0,0 @@
#name: Illegal RAS instruction use.
#source: illegal-ras-1.s
#as: -march=armv8-a -mno-verbose-error
#error_output: illegal-ras-1.l

37
gas/testsuite/gas/aarch64/illegal-ras-1.l
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@ -1,37 +0,0 @@
[^:]+: Assembler messages:
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'

50
gas/testsuite/gas/aarch64/illegal-ras-1.s
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@ -1,50 +0,0 @@
/* Incorrect use of the RAS extension instructions. */
.text
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
/* ARMv8-A. */
.arch armv8-a
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
/* ARMv8.1-A. */
.arch armv8.1-a
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0

3
gas/testsuite/gas/aarch64/illegal-sysreg-2.d
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@ -1,3 +0,0 @@
#as: -march=armv8-a
#source: sysreg-2.s
#error_output: illegal-sysreg-2.l

47
gas/testsuite/gas/aarch64/illegal-sysreg-2.l
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@ -1,47 +0,0 @@
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: selected processor does not support system register name 'id_aa64mmfr2_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvap'
[^:]*:[0-9]+: Error: selected processor does not support system register name 's1e1rp'
[^:]*:[0-9]+: Error: selected processor does not support system register name 's1e1wp'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmblimitr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmblimitr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmbptr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmbptr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmbsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmbsr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsicr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsicr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsirr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsirr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsfcr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsfcr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsevfr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsevfr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmslatfr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmslatfr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmscr_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmbidr_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'pmsidr_el1'

5
include/ChangeLog
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@ -1,3 +1,8 @@
2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_ARCH_V8): Add RAS to Armv8-A.
(AARCH64_ARCH_V8_2): Remove RAS from Armv8.2-A set.
2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_LS64): New +ls64 feature flag. * opcode/aarch64.h (AARCH64_FEATURE_LS64): New +ls64 feature flag.

4
include/opcode/aarch64.h
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@ -97,6 +97,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_V8_A \ AARCH64_FEATURE_V8_A \
| AARCH64_FEATURE_FP \ | AARCH64_FEATURE_FP \
| AARCH64_FEATURE_RAS \
| AARCH64_FEATURE_SIMD) | AARCH64_FEATURE_SIMD)
#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \ #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
AARCH64_FEATURE_CRC \ AARCH64_FEATURE_CRC \
@ -106,8 +107,7 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_LOR \ | AARCH64_FEATURE_LOR \
| AARCH64_FEATURE_RDMA) | AARCH64_FEATURE_RDMA)
#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \ #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
AARCH64_FEATURE_V8_2 \ AARCH64_FEATURE_V8_2)
| AARCH64_FEATURE_RAS)
#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \ #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
AARCH64_FEATURE_V8_3 \ AARCH64_FEATURE_V8_3 \
| AARCH64_FEATURE_RCPC \ | AARCH64_FEATURE_RCPC \

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-11-04 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 2020-11-03 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores. * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.

5
opcodes/aarch64-opc.c
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@ -4017,6 +4017,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0), SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0),
SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0), SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0),
SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0), SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0),
SR_RAS ("erxmisc2_el1", CPENC (3,0,C5,C5,2), 0),
SR_RAS ("erxmisc3_el1", CPENC (3,0,C5,C5,3), 0),
SR_RAS ("erxpfgcdn_el1", CPENC (3,0,C5,C4,6), 0),
SR_RAS ("erxpfgctl_el1", CPENC (3,0,C5,C4,5), 0),
SR_RAS ("erxpfgf_el1", CPENC (3,0,C5,C4,4), F_REG_READ),
SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0), SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0),
SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0), SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0),
SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0), SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0),