espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-27 14:39:09 +08:00
Code Issues Packages Projects Releases Wiki Activity

* config/tc-m32r.c (allow_m32rx): Must compile with K&R C.

Browse Source 
(m32rx support): only include #ifdef HAVE_CPU_M32RX.
This commit is contained in:
Doug Evans
1998-01-29 17:27:49 +00:00
parent 5ffc6deeb3
commit 55a4759f2b
1 changed files with 15 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
gas/config/tc-m32r.c
View File

@ -103,7 +103,8 @@ static struct m32r_hi_fixup * m32r_hi_fixup_list;
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
static void static void
allow_m32rx (int on) allow_m32rx (on)
int on;
{ {
enable_m32rx = on; enable_m32rx = on;
@ -381,6 +382,8 @@ md_begin ()
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
} }
#ifdef HAVE_CPU_M32RX
/* Returns non zero if the given instruction writes to a destination register. */ /* Returns non zero if the given instruction writes to a destination register. */
static int static int
writes_to_dest_reg (insn) writes_to_dest_reg (insn)
@ -676,6 +679,9 @@ assemble_parallel_insn (str, str2)
return; return;
} }
#endif /* HAVE_CPU_M32RX */
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
@ -691,12 +697,14 @@ md_assemble (str)
cgen_asm_init_parse (); cgen_asm_init_parse ();
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
#ifdef HAVE_CPU_M32RX
/* Look for a parallel instruction seperator. */ /* Look for a parallel instruction seperator. */
if ((str2 = strstr (str, "||")) != NULL) if ((str2 = strstr (str, "||")) != NULL)
{ {
assemble_parallel_insn (str, str2); assemble_parallel_insn (str, str2);
return; return;
} }
#endif
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg); insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
@ -707,11 +715,13 @@ md_assemble (str)
} }
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
#ifdef HAVE_CPU_M32RX
if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
{ {
as_bad ("instruction '%s' is for the M32RX only", str); as_bad ("instruction '%s' is for the M32RX only", str);
return; return;
} }
#endif
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
if (CGEN_INSN_BITSIZE (insn.insn) == 32) if (CGEN_INSN_BITSIZE (insn.insn) == 32)
@ -744,6 +754,7 @@ md_assemble (str)
{ {
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
/* start-sanitize-phase2-m32rx */ /* start-sanitize-phase2-m32rx */
#ifdef HAVE_CPU_M32RX
/* Look to see if this instruction can be combined with the /* Look to see if this instruction can be combined with the
previous instruction to make one, parallel, 32 bit instruction. previous instruction to make one, parallel, 32 bit instruction.
If the previous instruction (potentially) changed the flow of If the previous instruction (potentially) changed the flow of
@ -762,6 +773,7 @@ md_assemble (str)
else if (can_make_parallel (& insn, & prev_insn.insn) == NULL) else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
swap = true; swap = true;
} }
#endif
/* end-sanitize-phase2-m32rx */ /* end-sanitize-phase2-m32rx */
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
@ -779,6 +791,7 @@ md_assemble (str)
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
/* start-sanitize-phase2-m32rx */ /* start-sanitize-phase2-m32rx */
#ifdef HAVE_CPU_M32RX
if (swap) if (swap)
{ {
int tmp; int tmp;
@ -806,6 +819,7 @@ md_assemble (str)
/* Record where this instruction was assembled. */ /* Record where this instruction was assembled. */
prev_insn.addr = insn.addr; prev_insn.addr = insn.addr;
prev_insn.frag = insn.frag; prev_insn.frag = insn.frag;
#endif
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
/* If the insn needs the following one to be on a 32 bit boundary /* If the insn needs the following one to be on a 32 bit boundary