espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-08-06 06:45:56 +08:00
Code Issues Packages Projects Releases Wiki Activity

* mips-opc.c: Change div machine instruction to be z,s,t rather

Browse Source 
than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
This commit is contained in:
Ian Lance Taylor
1993-09-02 17:14:10 +00:00
parent fb27a96270
commit 547998d2c8
3 changed files with 23 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
opcodes/mips-dis.c
View File

@ -49,7 +49,7 @@ static CONST char * CONST reg_names[] = REGISTER_NAMES;
/* subroutine */
static void
print_insn_arg (d, l, pc, info)
char *d;
const char *d;
register unsigned long int l;
bfd_vma pc;
struct disassemble_info *info;
@ -114,6 +114,10 @@ print_insn_arg (d, l, pc, info)
reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
case 'z':
(*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
break;
case '<':
(*info->fprintf_func) (info->stream, "0x%x",
(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
@ -180,7 +184,7 @@ _print_insn_mips (memaddr, word, info)
unsigned long int word;
{
register int i;
register char *d;
register const char *d;
for (i = 0; i < NUMOPCODES; i++)
{