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RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place.

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For the ifunc symbol, which is referenced by GOT rather than PLT relocs,
we should add the dynamic reloc (usually IRELATIVE) into the .rel.iplt
when generating the static executable.  But if we use riscv_elf_append_rela
to add the dynamic relocs into .rela.iplt, this may cause the overwrite
problem.

The reason is that we don't handle the `reloc_index` of .rela.iplt, but
the riscv_elf_append_rela adds the relocs to the place that are calculated
from the reloc_index (in seqential).  Therefore, we may overwrite the
dynamic relocs when the `reloc_index` of .rela.iplt isn't handled correctly.

One solution is that we can add these dynamic relocs (GOT ifunc) from
the last of .rela.iplt section.  But I'm not sure if it is the best way.

	bfd/
	* elfnn-riscv.c (riscv_elf_link_hash_table): Add last_iplt_index.
	(riscv_elf_size_dynamic_sections): Initialize the last_iplt_index.
	(riscv_elf_relocate_section): Use riscv_elf_append_rela.
	(riscv_elf_finish_dynamic_symbol): If the use_elf_append_rela is
	false, then we should add the dynamic relocs from the last of
	the .rela.iplt, and don't use the riscv_elf_append_rela to add.

	ld/
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
This commit is contained in:
Nelson Chu
2020-10-06 20:48:23 -07:00
parent 02dd9d2568
commit 51a8a7c2e3
9 changed files with 140 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
ld/ChangeLog
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@ -1,3 +1,12 @@
2020-10-16 Nelson Chu <nelson.chu@sifive.com>
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2020-10-16 Nelson Chu <nelson.chu@sifive.com>
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.

4
ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd Normal file
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@ -0,0 +1,4 @@
Relocation section '.rela.plt' at .*
[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*

8
ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd Normal file
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@ -0,0 +1,8 @@
Relocation section '.rela.got' at .*
[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_(32|64)[ ]+foo2\(\)[ ]+foo2 \+ 0
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_(32|64)[ ]+foo1\(\)[ ]+foo1 \+ 0
#...
Relocation section '.rela.plt' at .*
[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_JUMP_SLOT[ ]+foo1\(\)[ ]+foo1 \+ 0

7
ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd Normal file
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@ -0,0 +1,7 @@
Relocation section '.rela.got' at .*
[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
Relocation section '.rela.plt' at .*
[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*

19
ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d Normal file
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@ -0,0 +1,19 @@
#...
Disassembly of section .plt:
#...
0+[0-9a-f]+ <(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>:
#...
Disassembly of section .text:
#...
0+[0-9a-f]+ <foo_resolver>:
#...
0+[0-9a-f]+ <bar>:
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|.*)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(.*plt.*)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(.*plt.*)>
.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|.*)>
#...

38
ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s Normal file
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@ -0,0 +1,38 @@
.text
.type foo_resolver, @function
foo_resolver:
ret
.size foo_resolver, .-foo_resolver
.globl foo1
.type foo1, %gnu_indirect_function
.set foo1, foo_resolver
.globl foo2
.type foo2, %gnu_indirect_function
.set foo2, foo_resolver
.globl bar
.type bar, @function
bar:
.L1:
auipc x1, %got_pcrel_hi (foo1)
.ifdef __64_bit__
ld x1, %pcrel_lo (.L1) (x1)
.else
lw x1, %pcrel_lo (.L1) (x1)
.endif
call foo1
call foo1@plt
.L2:
auipc x2, %got_pcrel_hi (foo2)
.ifdef __64_bit__
ld x2, %pcrel_lo (.L2) (x2)
.else
lw x2, %pcrel_lo (.L2) (x2)
.endif
ret
.size bar, .-bar

7
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
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@ -175,6 +175,13 @@ if [istarget "riscv*-*-*"] {
run_dump_test_ifunc "ifunc-plt-02" rv64 exe
run_dump_test_ifunc "ifunc-plt-02" rv64 pie
run_dump_test_ifunc "ifunc-plt-02" rv64 pic
# Check the .rela.iplt overwrite issue.
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 exe
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pie
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pic
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 exe
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pie
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pic
# Setup shared libraries.
run_ld_link_tests {