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[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.

Browse Source 
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
   <OP> <Hd>, <Hs>, #<imm>

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
	by immediate instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SSHIFT_H): New.
	(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
	and fcvtzu to the Adv.SIMD scalar shift by immediate group.

Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
This commit is contained in:
Matthew Wahab
2015-12-14 17:46:21 +00:00
parent b5b0f34c66
commit 4fd0a9fd00
8 changed files with 1090 additions and 1023 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
gas/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
2015-12-14 Matthew Wahab <matthew.wahab@arm.com> 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output. * gas/aarch64/advsimd-fp16.d: Update expected output.

16
gas/testsuite/gas/aarch64/advsimd-fp16.d
View File

@ -547,3 +547,19 @@ Disassembly of section \.text:
[0-9a-f]+: 6f1dfc41 fcvtzu v1.8h, v2.8h, #3 [0-9a-f]+: 6f1dfc41 fcvtzu v1.8h, v2.8h, #3
[0-9a-f]+: 2f1ffc00 fcvtzu v0.4h, v0.4h, #1 [0-9a-f]+: 2f1ffc00 fcvtzu v0.4h, v0.4h, #1
[0-9a-f]+: 6f1ffc00 fcvtzu v0.8h, v0.8h, #1 [0-9a-f]+: 6f1ffc00 fcvtzu v0.8h, v0.8h, #1
[0-9a-f]+: 5f7de441 scvtf d1, d2, #3
[0-9a-f]+: 5f3de441 scvtf s1, s2, #3
[0-9a-f]+: 5f1de441 scvtf h1, h2, #3
[0-9a-f]+: 5f1fe400 scvtf h0, h0, #1
[0-9a-f]+: 5f7dfc41 fcvtzs d1, d2, #3
[0-9a-f]+: 5f3dfc41 fcvtzs s1, s2, #3
[0-9a-f]+: 5f1dfc41 fcvtzs h1, h2, #3
[0-9a-f]+: 5f1ffc00 fcvtzs h0, h0, #1
[0-9a-f]+: 7f7de441 ucvtf d1, d2, #3
[0-9a-f]+: 7f3de441 ucvtf s1, s2, #3
[0-9a-f]+: 7f1de441 ucvtf h1, h2, #3
[0-9a-f]+: 7f1fe400 ucvtf h0, h0, #1
[0-9a-f]+: 7f7dfc41 fcvtzu d1, d2, #3
[0-9a-f]+: 7f3dfc41 fcvtzu s1, s2, #3
[0-9a-f]+: 7f1dfc41 fcvtzu h1, h2, #3
[0-9a-f]+: 7f1ffc00 fcvtzu h0, h0, #1

14
gas/testsuite/gas/aarch64/advsimd-fp16.s
View File

@ -244,3 +244,17 @@
shift_imm fcvtzs shift_imm fcvtzs
shift_imm ucvtf shift_imm ucvtf
shift_imm fcvtzu shift_imm fcvtzu
/* Adv.SIMD scalar shift by immediate. */
.macro sshift_imm, op
\op d1, d2, #3
\op s1, s2, #3
\op h1, h2, #3
\op h0, h0, #1
.endm
sshift_imm scvtf
sshift_imm fcvtzs
sshift_imm ucvtf
sshift_imm fcvtzu

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
2015-12-14 Matthew Wahab <matthew.wahab@arm.com> 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate. * aarch64-asm-2.c: Regenerate.

608
opcodes/aarch64-asm-2.c
View File

@ -111,334 +111,334 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 526: /* dup */ case 526: /* dup */
value = 526; /* --> dup. */ value = 526; /* --> dup. */
break; break;
case 610: /* sxtw */ case 614: /* sxtw */
case 609: /* sxth */ case 613: /* sxth */
case 608: /* sxtb */ case 612: /* sxtb */
case 611: /* asr */ case 615: /* asr */
case 607: /* sbfx */ case 611: /* sbfx */
case 606: /* sbfiz */ case 610: /* sbfiz */
case 605: /* sbfm */ case 609: /* sbfm */
value = 605; /* --> sbfm. */ value = 609; /* --> sbfm. */
break; break;
case 614: /* bfc */ case 618: /* bfc */
case 615: /* bfxil */ case 619: /* bfxil */
case 613: /* bfi */ case 617: /* bfi */
case 612: /* bfm */ case 616: /* bfm */
value = 612; /* --> bfm. */ value = 616; /* --> bfm. */
break; break;
case 620: /* uxth */ case 624: /* uxth */
case 619: /* uxtb */ case 623: /* uxtb */
case 622: /* lsr */ case 626: /* lsr */
case 621: /* lsl */ case 625: /* lsl */
case 618: /* ubfx */ case 622: /* ubfx */
case 617: /* ubfiz */ case 621: /* ubfiz */
case 616: /* ubfm */ case 620: /* ubfm */
value = 616; /* --> ubfm. */ value = 620; /* --> ubfm. */
break; break;
case 640: /* cset */ case 644: /* cset */
case 639: /* cinc */ case 643: /* cinc */
case 638: /* csinc */ case 642: /* csinc */
value = 638; /* --> csinc. */ value = 642; /* --> csinc. */
break; break;
case 643: /* csetm */ case 647: /* csetm */
case 642: /* cinv */ case 646: /* cinv */
case 641: /* csinv */ case 645: /* csinv */
value = 641; /* --> csinv. */ value = 645; /* --> csinv. */
break; break;
case 645: /* cneg */ case 649: /* cneg */
case 644: /* csneg */ case 648: /* csneg */
value = 644; /* --> csneg. */ value = 648; /* --> csneg. */
break; break;
case 663: /* rev */ case 667: /* rev */
case 664: /* rev64 */ case 668: /* rev64 */
value = 663; /* --> rev. */ value = 667; /* --> rev. */
break; break;
case 671: /* lsl */ case 675: /* lsl */
case 670: /* lslv */ case 674: /* lslv */
value = 670; /* --> lslv. */ value = 674; /* --> lslv. */
break; break;
case 673: /* lsr */ case 677: /* lsr */
case 672: /* lsrv */ case 676: /* lsrv */
value = 672; /* --> lsrv. */ value = 676; /* --> lsrv. */
break; break;
case 675: /* asr */ case 679: /* asr */
case 674: /* asrv */ case 678: /* asrv */
value = 674; /* --> asrv. */ value = 678; /* --> asrv. */
break; break;
case 677: /* ror */ case 681: /* ror */
case 676: /* rorv */ case 680: /* rorv */
value = 676; /* --> rorv. */ value = 680; /* --> rorv. */
break; break;
case 687: /* mul */ case 691: /* mul */
case 686: /* madd */ case 690: /* madd */
value = 686; /* --> madd. */ value = 690; /* --> madd. */
break; break;
case 689: /* mneg */ case 693: /* mneg */
case 688: /* msub */ case 692: /* msub */
value = 688; /* --> msub. */ value = 692; /* --> msub. */
break; break;
case 691: /* smull */ case 695: /* smull */
case 690: /* smaddl */ case 694: /* smaddl */
value = 690; /* --> smaddl. */ value = 694; /* --> smaddl. */
break; break;
case 693: /* smnegl */ case 697: /* smnegl */
case 692: /* smsubl */ case 696: /* smsubl */
value = 692; /* --> smsubl. */ value = 696; /* --> smsubl. */
break; break;
case 696: /* umull */ case 700: /* umull */
case 695: /* umaddl */ case 699: /* umaddl */
value = 695; /* --> umaddl. */ value = 699; /* --> umaddl. */
break; break;
case 698: /* umnegl */ case 702: /* umnegl */
case 697: /* umsubl */ case 701: /* umsubl */
value = 697; /* --> umsubl. */ value = 701; /* --> umsubl. */
break; break;
case 709: /* ror */ case 713: /* ror */
case 708: /* extr */ case 712: /* extr */
value = 708; /* --> extr. */ value = 712; /* --> extr. */
break; break;
case 916: /* bic */ case 920: /* bic */
case 915: /* and */ case 919: /* and */
value = 915; /* --> and. */ value = 919; /* --> and. */
break; break;
case 918: /* mov */ case 922: /* mov */
case 917: /* orr */ case 921: /* orr */
value = 917; /* --> orr. */ value = 921; /* --> orr. */
break; break;
case 921: /* tst */ case 925: /* tst */
case 920: /* ands */ case 924: /* ands */
value = 920; /* --> ands. */ value = 924; /* --> ands. */
break; break;
case 926: /* uxtw */ case 930: /* uxtw */
case 925: /* mov */ case 929: /* mov */
case 924: /* orr */ case 928: /* orr */
value = 924; /* --> orr. */ value = 928; /* --> orr. */
break; break;
case 928: /* mvn */ case 932: /* mvn */
case 927: /* orn */ case 931: /* orn */
value = 927; /* --> orn. */ value = 931; /* --> orn. */
break; break;
case 932: /* tst */ case 936: /* tst */
case 931: /* ands */ case 935: /* ands */
value = 931; /* --> ands. */ value = 935; /* --> ands. */
break; break;
case 1058: /* staddb */ case 1062: /* staddb */
case 962: /* ldaddb */ case 966: /* ldaddb */
value = 962; /* --> ldaddb. */ value = 966; /* --> ldaddb. */
break; break;
case 1059: /* staddh */ case 1063: /* staddh */
case 963: /* ldaddh */ case 967: /* ldaddh */
value = 963; /* --> ldaddh. */ value = 967; /* --> ldaddh. */
break; break;
case 1060: /* stadd */ case 1064: /* stadd */
case 964: /* ldadd */ case 968: /* ldadd */
value = 964; /* --> ldadd. */ value = 968; /* --> ldadd. */
break; break;
case 1061: /* staddlb */ case 1065: /* staddlb */
case 966: /* ldaddlb */ case 970: /* ldaddlb */
value = 966; /* --> ldaddlb. */ value = 970; /* --> ldaddlb. */
break; break;
case 1062: /* staddlh */ case 1066: /* staddlh */
case 969: /* ldaddlh */ case 973: /* ldaddlh */
value = 969; /* --> ldaddlh. */ value = 973; /* --> ldaddlh. */
break; break;
case 1063: /* staddl */ case 1067: /* staddl */
case 972: /* ldaddl */ case 976: /* ldaddl */
value = 972; /* --> ldaddl. */ value = 976; /* --> ldaddl. */
break; break;
case 1064: /* stclrb */ case 1068: /* stclrb */
case 974: /* ldclrb */ case 978: /* ldclrb */
value = 974; /* --> ldclrb. */ value = 978; /* --> ldclrb. */
break; break;
case 1065: /* stclrh */ case 1069: /* stclrh */
case 975: /* ldclrh */ case 979: /* ldclrh */
value = 975; /* --> ldclrh. */ value = 979; /* --> ldclrh. */
break; break;
case 1066: /* stclr */ case 1070: /* stclr */
case 976: /* ldclr */ case 980: /* ldclr */
value = 976; /* --> ldclr. */ value = 980; /* --> ldclr. */
break; break;
case 1067: /* stclrlb */ case 1071: /* stclrlb */
case 978: /* ldclrlb */ case 982: /* ldclrlb */
value = 978; /* --> ldclrlb. */ value = 982; /* --> ldclrlb. */
break; break;
case 1068: /* stclrlh */ case 1072: /* stclrlh */
case 981: /* ldclrlh */ case 985: /* ldclrlh */
value = 981; /* --> ldclrlh. */ value = 985; /* --> ldclrlh. */
break; break;
case 1069: /* stclrl */ case 1073: /* stclrl */
case 984: /* ldclrl */ case 988: /* ldclrl */
value = 984; /* --> ldclrl. */ value = 988; /* --> ldclrl. */
break; break;
case 1070: /* steorb */ case 1074: /* steorb */
case 986: /* ldeorb */ case 990: /* ldeorb */
value = 986; /* --> ldeorb. */ value = 990; /* --> ldeorb. */
break; break;
case 1071: /* steorh */ case 1075: /* steorh */
case 987: /* ldeorh */ case 991: /* ldeorh */
value = 987; /* --> ldeorh. */ value = 991; /* --> ldeorh. */
break; break;
case 1072: /* steor */ case 1076: /* steor */
case 988: /* ldeor */ case 992: /* ldeor */
value = 988; /* --> ldeor. */ value = 992; /* --> ldeor. */
break; break;
case 1073: /* steorlb */ case 1077: /* steorlb */
case 990: /* ldeorlb */ case 994: /* ldeorlb */
value = 990; /* --> ldeorlb. */ value = 994; /* --> ldeorlb. */
break; break;
case 1074: /* steorlh */ case 1078: /* steorlh */
case 993: /* ldeorlh */ case 997: /* ldeorlh */
value = 993; /* --> ldeorlh. */ value = 997; /* --> ldeorlh. */
break; break;
case 1075: /* steorl */ case 1079: /* steorl */
case 996: /* ldeorl */ case 1000: /* ldeorl */
value = 996; /* --> ldeorl. */ value = 1000; /* --> ldeorl. */
break; break;
case 1076: /* stsetb */ case 1080: /* stsetb */
case 998: /* ldsetb */ case 1002: /* ldsetb */
value = 998; /* --> ldsetb. */ value = 1002; /* --> ldsetb. */
break; break;
case 1077: /* stseth */ case 1081: /* stseth */
case 999: /* ldseth */ case 1003: /* ldseth */
value = 999; /* --> ldseth. */ value = 1003; /* --> ldseth. */
break; break;
case 1078: /* stset */ case 1082: /* stset */
case 1000: /* ldset */ case 1004: /* ldset */
value = 1000; /* --> ldset. */ value = 1004; /* --> ldset. */
break; break;
case 1079: /* stsetlb */ case 1083: /* stsetlb */
case 1002: /* ldsetlb */ case 1006: /* ldsetlb */
value = 1002; /* --> ldsetlb. */ value = 1006; /* --> ldsetlb. */
break; break;
case 1080: /* stsetlh */ case 1084: /* stsetlh */
case 1005: /* ldsetlh */ case 1009: /* ldsetlh */
value = 1005; /* --> ldsetlh. */ value = 1009; /* --> ldsetlh. */
break; break;
case 1081: /* stsetl */ case 1085: /* stsetl */
case 1008: /* ldsetl */ case 1012: /* ldsetl */
value = 1008; /* --> ldsetl. */ value = 1012; /* --> ldsetl. */
break; break;
case 1082: /* stsmaxb */ case 1086: /* stsmaxb */
case 1010: /* ldsmaxb */ case 1014: /* ldsmaxb */
value = 1010; /* --> ldsmaxb. */ value = 1014; /* --> ldsmaxb. */
break; break;
case 1083: /* stsmaxh */ case 1087: /* stsmaxh */
case 1011: /* ldsmaxh */ case 1015: /* ldsmaxh */
value = 1011; /* --> ldsmaxh. */ value = 1015; /* --> ldsmaxh. */
break; break;
case 1084: /* stsmax */ case 1088: /* stsmax */
case 1012: /* ldsmax */ case 1016: /* ldsmax */
value = 1012; /* --> ldsmax. */ value = 1016; /* --> ldsmax. */
break; break;
case 1085: /* stsmaxlb */ case 1089: /* stsmaxlb */
case 1014: /* ldsmaxlb */ case 1018: /* ldsmaxlb */
value = 1014; /* --> ldsmaxlb. */ value = 1018; /* --> ldsmaxlb. */
break; break;
case 1086: /* stsmaxlh */ case 1090: /* stsmaxlh */
case 1017: /* ldsmaxlh */ case 1021: /* ldsmaxlh */
value = 1017; /* --> ldsmaxlh. */ value = 1021; /* --> ldsmaxlh. */
break; break;
case 1087: /* stsmaxl */ case 1091: /* stsmaxl */
case 1020: /* ldsmaxl */ case 1024: /* ldsmaxl */
value = 1020; /* --> ldsmaxl. */ value = 1024; /* --> ldsmaxl. */
break; break;
case 1088: /* stsminb */ case 1092: /* stsminb */
case 1022: /* ldsminb */ case 1026: /* ldsminb */
value = 1022; /* --> ldsminb. */ value = 1026; /* --> ldsminb. */
break; break;
case 1089: /* stsminh */ case 1093: /* stsminh */
case 1023: /* ldsminh */ case 1027: /* ldsminh */
value = 1023; /* --> ldsminh. */ value = 1027; /* --> ldsminh. */
break; break;
case 1090: /* stsmin */ case 1094: /* stsmin */
case 1024: /* ldsmin */ case 1028: /* ldsmin */
value = 1024; /* --> ldsmin. */ value = 1028; /* --> ldsmin. */
break; break;
case 1091: /* stsminlb */ case 1095: /* stsminlb */
case 1026: /* ldsminlb */ case 1030: /* ldsminlb */
value = 1026; /* --> ldsminlb. */ value = 1030; /* --> ldsminlb. */
break; break;
case 1092: /* stsminlh */ case 1096: /* stsminlh */
case 1029: /* ldsminlh */ case 1033: /* ldsminlh */
value = 1029; /* --> ldsminlh. */ value = 1033; /* --> ldsminlh. */
break; break;
case 1093: /* stsminl */ case 1097: /* stsminl */
case 1032: /* ldsminl */ case 1036: /* ldsminl */
value = 1032; /* --> ldsminl. */ value = 1036; /* --> ldsminl. */
break; break;
case 1094: /* stumaxb */ case 1098: /* stumaxb */
case 1034: /* ldumaxb */ case 1038: /* ldumaxb */
value = 1034; /* --> ldumaxb. */ value = 1038; /* --> ldumaxb. */
break; break;
case 1095: /* stumaxh */ case 1099: /* stumaxh */
case 1035: /* ldumaxh */ case 1039: /* ldumaxh */
value = 1035; /* --> ldumaxh. */ value = 1039; /* --> ldumaxh. */
break; break;
case 1096: /* stumax */ case 1100: /* stumax */
case 1036: /* ldumax */ case 1040: /* ldumax */
value = 1036; /* --> ldumax. */ value = 1040; /* --> ldumax. */
break; break;
case 1097: /* stumaxlb */ case 1101: /* stumaxlb */
case 1038: /* ldumaxlb */ case 1042: /* ldumaxlb */
value = 1038; /* --> ldumaxlb. */ value = 1042; /* --> ldumaxlb. */
break; break;
case 1098: /* stumaxlh */ case 1102: /* stumaxlh */
case 1041: /* ldumaxlh */ case 1045: /* ldumaxlh */
value = 1041; /* --> ldumaxlh. */ value = 1045; /* --> ldumaxlh. */
break; break;
case 1099: /* stumaxl */ case 1103: /* stumaxl */
case 1044: /* ldumaxl */ case 1048: /* ldumaxl */
value = 1044; /* --> ldumaxl. */ value = 1048; /* --> ldumaxl. */
break; break;
case 1100: /* stuminb */ case 1104: /* stuminb */
case 1046: /* lduminb */ case 1050: /* lduminb */
value = 1046; /* --> lduminb. */ value = 1050; /* --> lduminb. */
break; break;
case 1101: /* stuminh */ case 1105: /* stuminh */
case 1047: /* lduminh */ case 1051: /* lduminh */
value = 1047; /* --> lduminh. */ value = 1051; /* --> lduminh. */
break; break;
case 1102: /* stumin */ case 1106: /* stumin */
case 1048: /* ldumin */ case 1052: /* ldumin */
value = 1048; /* --> ldumin. */ value = 1052; /* --> ldumin. */
break; break;
case 1103: /* stuminlb */ case 1107: /* stuminlb */
case 1050: /* lduminlb */ case 1054: /* lduminlb */
value = 1050; /* --> lduminlb. */ value = 1054; /* --> lduminlb. */
break; break;
case 1104: /* stuminlh */ case 1108: /* stuminlh */
case 1053: /* lduminlh */ case 1057: /* lduminlh */
value = 1053; /* --> lduminlh. */ value = 1057; /* --> lduminlh. */
break; break;
case 1105: /* stuminl */ case 1109: /* stuminl */
case 1056: /* lduminl */ case 1060: /* lduminl */
value = 1056; /* --> lduminl. */ value = 1060; /* --> lduminl. */
break; break;
case 1107: /* mov */ case 1111: /* mov */
case 1106: /* movn */ case 1110: /* movn */
value = 1106; /* --> movn. */ value = 1110; /* --> movn. */
break; break;
case 1109: /* mov */ case 1113: /* mov */
case 1108: /* movz */ case 1112: /* movz */
value = 1108; /* --> movz. */ value = 1112; /* --> movz. */
break; break;
case 1122: /* psb */ case 1126: /* psb */
case 1121: /* esb */ case 1125: /* esb */
case 1120: /* sevl */ case 1124: /* sevl */
case 1119: /* sev */ case 1123: /* sev */
case 1118: /* wfi */ case 1122: /* wfi */
case 1117: /* wfe */ case 1121: /* wfe */
case 1116: /* yield */ case 1120: /* yield */
case 1115: /* nop */ case 1119: /* nop */
case 1114: /* hint */ case 1118: /* hint */
value = 1114; /* --> hint. */ value = 1118; /* --> hint. */
break; break;
case 1131: /* tlbi */ case 1135: /* tlbi */
case 1130: /* ic */ case 1134: /* ic */
case 1129: /* dc */ case 1133: /* dc */
case 1128: /* at */ case 1132: /* at */
case 1127: /* sys */ case 1131: /* sys */
value = 1127; /* --> sys. */ value = 1131; /* --> sys. */
break; break;
default: return NULL; default: return NULL;
} }

1356
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

90
opcodes/aarch64-opc-2.c
View File

@ -122,70 +122,70 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] = static const unsigned op_enum_table [] =
{ {
0, 0,
824, 828,
825,
826,
829, 829,
830, 830,
831,
832,
833, 833,
827,
828,
834, 834,
835, 835,
857, 836,
858, 837,
859, 831,
832,
838,
839,
861,
862, 862,
863, 863,
864,
865,
866, 866,
860,
861,
867, 867,
868, 868,
911, 869,
912, 870,
913, 864,
914, 865,
871,
872,
915,
916,
917,
918,
12, 12,
627,
628,
1110,
1112,
1114,
922,
1113,
1111,
311,
615,
626,
625,
920,
622,
619,
611,
610,
617,
618,
621,
623, 623,
624, 624,
1106, 930,
1108,
1110,
918,
1109,
1107,
311,
611,
622,
621,
916,
618,
615,
607,
606,
613,
614,
617,
619,
620,
926,
639,
642,
645,
640,
643, 643,
768, 646,
649,
644,
647,
772,
171, 171,
172, 172,
173, 173,
174, 174,
507, 507,
709, 713,
380, 380,
382, 382,
404, 404,

14
opcodes/aarch64-tbl.h
View File

@ -375,6 +375,12 @@
QLF3(S_D , S_D , S_D ) \ QLF3(S_D , S_D , S_D ) \
} }
/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
#define QL_SSHIFT_H \
{ \
QLF3 (S_H, S_H, S_H) \
}
/* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */ /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
#define QL_SSHIFTN \ #define QL_SSHIFTN \
{ \ { \
@ -2106,7 +2112,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
{"scvtf", 0x5f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
{"fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0}, {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
@ -2120,7 +2130,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0}, {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
{"ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0}, {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
{"fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
/* Bitfield. */ /* Bitfield. */
{"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N}, {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV}, {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},