mirror of
https://github.com/espressif/binutils-gdb.git
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Added Files:
bigmips64.mt idt64.mt idtl64.mt littlemips64.mt tm-bigmips64.h tm-idt64.h tm-idtl64.h tm-mips64.h Add the above files to support mips 64 bits target.
This commit is contained in:
Kung Hsu
3
gdb/config/mips/bigmips64.mt
Normal file
3
gdb/config/mips/bigmips64.mt
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@ -0,0 +1,3 @@
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# Target: Big-endian MIPS machine such as Sony News
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TDEPFILES= mips-pinsn.o mips-tdep.o exec.o
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TM_FILE= tm-bigmips64.h
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3
gdb/config/mips/idt64.mt
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3
gdb/config/mips/idt64.mt
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@ -0,0 +1,3 @@
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# Target: Big-endian IDT board.
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TDEPFILES= mips-pinsn.o mips-tdep.o exec.o remote-mips.o
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TM_FILE= tm-idt64.h
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3
gdb/config/mips/idtl64.mt
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3
gdb/config/mips/idtl64.mt
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@ -0,0 +1,3 @@
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# Target: Big-endian IDT board.
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TDEPFILES= mips-pinsn.o mips-tdep.o exec.o remote-mips.o
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TM_FILE= tm-idtl64.h
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3
gdb/config/mips/littlemips64.mt
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3
gdb/config/mips/littlemips64.mt
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@ -0,0 +1,3 @@
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# Target: Little-endian MIPS machine such as DECstation.
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TDEPFILES= mips-pinsn.o mips-tdep.o exec.o
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TM_FILE= tm-mips64.h
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32
gdb/config/mips/tm-bigmips64.h
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32
gdb/config/mips/tm-bigmips64.h
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@ -0,0 +1,32 @@
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/* Target machine parameters for MIPS r4000
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Copyright 1994 Free Software Foundation, Inc.
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Contributed by Ian Lance Taylor (ian@cygnus.com)
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#define GDB_TARGET_IS_MIPS64
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/* Use eight byte registers. */
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#define MIPS_REGSIZE 8
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/* Load double words in CALL_DUMMY. */
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#define OP_LDFPR 065 /* ldc1 */
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#define OP_LDGPR 067 /* ld */
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/* Get the basic MIPS definitions. Default to big endian, since that
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is how the chips are mostly used. */
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#include "tm-bigmips.h"
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25
gdb/config/mips/tm-idt64.h
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25
gdb/config/mips/tm-idt64.h
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@ -0,0 +1,25 @@
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/* Copyright (C) 1993 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "mips/tm-bigmips64.h"
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/* The IDT board uses an unusual breakpoint value, and sometimes gets
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confused when it sees the usual MIPS breakpoint instruction. */
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#undef BREAKPOINT
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#define BREAKPOINT {0, 0, 0x0a, 0x0d}
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25
gdb/config/mips/tm-idtl64.h
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25
gdb/config/mips/tm-idtl64.h
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@ -0,0 +1,25 @@
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/* Copyright (C) 1993 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "mips/tm-mips64.h"
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/* The IDT board uses an unusual breakpoint value, and sometimes gets
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confused when it sees the usual MIPS breakpoint instruction. */
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#undef BREAKPOINT
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#define BREAKPOINT {0x0d, 0x0a, 0, 0}
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@ -89,6 +89,14 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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#define REGISTER_SIZE 4
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/* The size of a register. This is predefined in tm-mips64.h. We
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can't use REGISTER_SIZE because that is used for various other
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things. */
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#ifndef MIPS_REGSIZE
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#define MIPS_REGSIZE 4
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#endif
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/* Number of machine registers */
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#define NUM_REGS 80
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@ -142,22 +150,22 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_BYTES (NUM_REGS*4)
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#define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define REGISTER_BYTE(N) ((N) * 4)
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#define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
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/* Number of bytes of storage in the actual machine representation
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for register N. On mips, all regs are 4 bytes. */
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for register N. On mips, all regs are the same size. */
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#define REGISTER_RAW_SIZE(N) 4
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#define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
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/* Number of bytes of storage in the program's representation
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for register N. On mips, all regs are 4 bytes. */
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for register N. On mips, all regs are the same size. */
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#define REGISTER_VIRTUAL_SIZE(N) 4
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#define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
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/* Largest value REGISTER_RAW_SIZE can have. */
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@ -299,25 +307,31 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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#define POP_FRAME mips_pop_frame()
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#define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
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#ifndef OP_LDFPR
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#define OP_LDFPR 061 /* lwc1 */
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#endif
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#ifndef OP_LDGPR
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#define OP_LDGPR 043 /* lw */
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#endif
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#define CALL_DUMMY_SIZE (16*4)
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#define Dest_Reg 2
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#define CALL_DUMMY {\
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MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
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0, /* nop # ... to stop raw backtrace*/\
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0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
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/* Start here: */\
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MK_OP(061,SP_REGNUM,12,0), /* lwc1 $f12,0(sp) # Reload FP regs*/\
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MK_OP(061,SP_REGNUM,13,4), /* lwc1 $f13,4(sp) */\
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MK_OP(061,SP_REGNUM,14,8), /* lwc1 $f14,8(sp) */\
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MK_OP(061,SP_REGNUM,15,12), /* lwc1 $f15,12(sp) */\
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MK_OP(043,SP_REGNUM,4,0), /* lw $r4,0(sp) # Reload first 4 args*/\
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MK_OP(043,SP_REGNUM,5,4), /* lw $r5,4(sp) */\
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MK_OP(043,SP_REGNUM,6,8), /* lw $r6,8(sp) */\
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MK_OP(043,SP_REGNUM,7,12), /* lw $r7,12(sp) */\
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/* Start here; reload FP regs, then GP regs: */\
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MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
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MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
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(017<<26)| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
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MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
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(Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\
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MK_OP(043,SP_REGNUM,7,12), /* lw $r7,12(sp) */\
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MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
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0x5000d, /* bpt */\
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}
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@ -328,7 +342,7 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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/* Insert the specified number of args and function address
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into a call sequence of the above form stored at DUMMYNAME. */
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#if TARGET_BYTE_ORDER == BIG_ENDIAN
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#if TARGET_BYTE_ORDER == BIG_ENDIAN && ! defined (GDB_TARGET_IS_MIPS64)
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/* For big endian mips machines the loading of FP values depends on whether
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they are single or double precision. */
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#define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
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@ -342,14 +356,14 @@ extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
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if (nargs > 0 && \
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TYPE_CODE(VALUE_TYPE(args[0])) == TYPE_CODE_FLT && \
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TYPE_LENGTH(VALUE_TYPE(args[0])) == 8) { \
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((int *) (dummyname))[3] = MK_OP(061,SP_REGNUM,12,4); \
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((int *) (dummyname))[4] = MK_OP(061,SP_REGNUM,13,0); \
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((int *) (dummyname))[3] = MK_OP(OP_LDFPR,SP_REGNUM,12,4); \
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((int *) (dummyname))[4] = MK_OP(OP_LDFPR,SP_REGNUM,13,0); \
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} \
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if (nargs > 1 && \
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TYPE_CODE(VALUE_TYPE(args[1])) == TYPE_CODE_FLT && \
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TYPE_LENGTH(VALUE_TYPE(args[1])) == 8) { \
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((int *) (dummyname))[5] = MK_OP(061,SP_REGNUM,14,12); \
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((int *) (dummyname))[6] = MK_OP(061,SP_REGNUM,15,8); \
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((int *) (dummyname))[5] = MK_OP(OP_LDFPR,SP_REGNUM,14,12); \
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((int *) (dummyname))[6] = MK_OP(OP_LDFPR,SP_REGNUM,15,8); \
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} \
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} \
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} while (0)
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32
gdb/config/mips/tm-mips64.h
Normal file
32
gdb/config/mips/tm-mips64.h
Normal file
@ -0,0 +1,32 @@
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/* Target machine parameters for MIPS r4000
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Copyright 1994 Free Software Foundation, Inc.
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Contributed by Ian Lance Taylor (ian@cygnus.com)
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
|
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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GNU General Public License for more details.
|
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|
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You should have received a copy of the GNU General Public License
|
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along with this program; if not, write to the Free Software
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||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#define GDB_TARGET_IS_MIPS64
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/* Use eight byte registers. */
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#define MIPS_REGSIZE 8
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/* Load double words in CALL_DUMMY. */
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#define OP_LDFPR 065 /* ldc1 */
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#define OP_LDGPR 067 /* ld */
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/* Get the basic MIPS definitions. Default to big endian, since that
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is how the chips are mostly used. */
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#include "tm-mips.h"
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