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* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.

Browse Source 
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask.  Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
This commit is contained in:
Alexandre Oliva
2000-07-04 06:06:30 +00:00
parent 8de8f17e3d
commit 4ef2594f4e
4 changed files with 40 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
sim/arm/ChangeLog
View File

@ -1,5 +1,13 @@
2000-07-04 Alexandre Oliva <aoliva@redhat.com> 2000-07-04 Alexandre Oliva <aoliva@redhat.com>
* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
* armemu.c (ARMul_Emulate): Compute writeback value before * armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination loading, since the offset register may be the destination
register. register.

8
sim/arm/armemu.c
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@ -1113,7 +1113,7 @@ ARMul_Emulate26 (register ARMul_State * state)
} }
} }
#endif #endif
if (DESTReg == 15 && BITS (17, 18) == 0) if (DESTReg == 15)
{ /* MSR reg to CPSR */ { /* MSR reg to CPSR */
UNDEF_MSRPC; UNDEF_MSRPC;
temp = DPRegRHS; temp = DPRegRHS;
@ -1241,7 +1241,7 @@ ARMul_Emulate26 (register ARMul_State * state)
break; break;
} }
#endif #endif
if (DESTReg == 15 && BITS (17, 18) == 0) if (DESTReg == 15)
{ /* MSR */ { /* MSR */
UNDEF_MSRPC; UNDEF_MSRPC;
ARMul_FixSPSR (state, instr, DPRegRHS); ARMul_FixSPSR (state, instr, DPRegRHS);
@ -1590,7 +1590,7 @@ ARMul_Emulate26 (register ARMul_State * state)
break; break;
case 0x32: /* TEQ immed and MSR immed to CPSR */ case 0x32: /* TEQ immed and MSR immed to CPSR */
if (DESTReg == 15 && BITS (17, 18) == 0) if (DESTReg == 15)
{ /* MSR immed to CPSR */ { /* MSR immed to CPSR */
ARMul_FixCPSR (state, instr, DPImmRHS); ARMul_FixCPSR (state, instr, DPImmRHS);
} }
@ -1655,7 +1655,7 @@ ARMul_Emulate26 (register ARMul_State * state)
break; break;
case 0x36: /* CMN immed and MSR immed to SPSR */ case 0x36: /* CMN immed and MSR immed to SPSR */
if (DESTReg == 15 && BITS (17, 18) == 0) /* MSR */ if (DESTReg == 15) /* MSR */
ARMul_FixSPSR (state, instr, DPImmRHS); ARMul_FixSPSR (state, instr, DPImmRHS);
else else
{ {

12
sim/arm/armemu.h
View File

@ -102,6 +102,11 @@ extern ARMword isize;
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)
#define CCBITS (0xf0000000L) #define CCBITS (0xf0000000L)
#define INTBITS (0xc0L) #define INTBITS (0xc0L)
@ -159,9 +164,10 @@ extern ARMword isize;
#endif #endif
#define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ; #define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
#define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS) #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS)) #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS) #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \ #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \ state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
ASSIGNN((state->Reg[15] & NBIT) != 0) ; \ ASSIGNN((state->Reg[15] & NBIT) != 0) ; \

42
sim/arm/armsupp.c
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@ -193,8 +193,7 @@ ARMul_GetCPSR (ARMul_State * state)
void void
ARMul_SetCPSR (ARMul_State * state, ARMword value) ARMul_SetCPSR (ARMul_State * state, ARMword value)
{ {
state->Cpsr = CPSR; state->Cpsr = value;
SETPSR (state->Cpsr, value);
ARMul_CPSRAltered (state); ARMul_CPSRAltered (state);
} }
@ -207,22 +206,17 @@ void
ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
{ {
state->Cpsr = CPSR; state->Cpsr = CPSR;
if (state->Bank == USERBANK) if (state->Bank != USERBANK)
{ /* Only write flags in user mode */ { /* In user mode, only write flags */
if (BIT (19)) if (BIT (16))
{ SETPSR_C (state->Cpsr, rhs);
SETCC (state->Cpsr, rhs); if (BIT (17))
} SETPSR_X (state->Cpsr, rhs);
} if (BIT (18))
else SETPSR_S (state->Cpsr, rhs);
{ /* Not a user mode */
if (BITS (16, 19) == 9)
SETPSR (state->Cpsr, rhs);
else if (BIT (16))
SETINTMODE (state->Cpsr, rhs);
else if (BIT (19))
SETCC (state->Cpsr, rhs);
} }
if (BIT (19))
SETPSR_F (state->Cpsr, rhs);
ARMul_CPSRAltered (state); ARMul_CPSRAltered (state);
} }
@ -263,12 +257,14 @@ ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
{ {
if (BANK_CAN_ACCESS_SPSR (state->Bank)) if (BANK_CAN_ACCESS_SPSR (state->Bank))
{ {
if (BITS (16, 19) == 9) if (BIT (16))
SETPSR (state->Spsr[state->Bank], rhs); SETPSR_C (state->Spsr[state->Bank], rhs);
else if (BIT (16)) if (BIT (17))
SETINTMODE (state->Spsr[state->Bank], rhs); SETPSR_X (state->Spsr[state->Bank], rhs);
else if (BIT (19)) if (BIT (18))
SETCC (state->Spsr[state->Bank], rhs); SETPSR_S (state->Spsr[state->Bank], rhs);
if (BIT (19))
SETPSR_F (state->Spsr[state->Bank], rhs);
} }
} }