mirror of
https://github.com/espressif/binutils-gdb.git
synced 2025-06-19 09:14:14 +08:00
MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK
Complement commit e407c74b5b60 ("Support for MIPS R5900 (Sony Playstation 2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and commit 2c62985659da ("MIPS: Add Octeon 3 support") and update the chip mask accordingly. include/ * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
This commit is contained in:
@ -1,3 +1,7 @@
|
|||||||
|
2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
||||||
|
|
||||||
|
* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
|
||||||
|
|
||||||
2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
|
||||||
|
|
||||||
* opcode/mips.h (ASE_DSPR3): Add a comment.
|
* opcode/mips.h (ASE_DSPR3): Add a comment.
|
||||||
|
@ -1194,7 +1194,7 @@ static const unsigned int mips_isa_table[] = {
|
|||||||
#undef ISAF
|
#undef ISAF
|
||||||
|
|
||||||
/* Masks used for Chip specific instructions. */
|
/* Masks used for Chip specific instructions. */
|
||||||
#define INSN_CHIP_MASK 0xc3ff0f20
|
#define INSN_CHIP_MASK 0xc3ff4f60
|
||||||
|
|
||||||
/* Cavium Networks Octeon instructions. */
|
/* Cavium Networks Octeon instructions. */
|
||||||
#define INSN_OCTEON 0x00000800
|
#define INSN_OCTEON 0x00000800
|
||||||
|
Reference in New Issue
Block a user