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RISC-V: Add T-Head Fmv vendor extension

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This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
2022-11-13 16:59:20 +01:00
committed by Nelson Chu
parent 7a4ce4a1bc
commit 4a3bc79bf4
8 changed files with 40 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
bfd/elfxx-riscv.c
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@ -1239,6 +1239,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadcmo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadfmv", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@ -2419,6 +2420,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xtheadcondmov");
case INSN_CLASS_XTHEADFMEMIDX:
return riscv_subset_supports (rps, "xtheadfmemidx");
case INSN_CLASS_XTHEADFMV:
return riscv_subset_supports (rps, "xtheadfmv");
case INSN_CLASS_XTHEADMAC:
return riscv_subset_supports (rps, "xtheadmac");
case INSN_CLASS_XTHEADMEMIDX:
@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xtheadcondmov";
case INSN_CLASS_XTHEADFMEMIDX:
return "xtheadfmemidx";
case INSN_CLASS_XTHEADFMV:
return "xtheadfmv";
case INSN_CLASS_XTHEADMAC:
return "xtheadmac";
case INSN_CLASS_XTHEADMEMIDX:

6
gas/NEWS
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@ -26,9 +26,9 @@
for --enable-compressed-debug-sections.
* Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs,
XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadMemIdx, XTheadMemPair,
XTheadMac, and XTheadSync) from version 2.0 of the T-Head ISA manual, which
are implemented in the Allwinner D1.
XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx,
XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head
ISA manual, which are implemented in the Allwinner D1.
* Add support for the RISC-V Zawrs extension, version 1.0-rc4.

5
gas/doc/c-riscv.texi
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@ -734,6 +734,11 @@ The XTheadFMemIdx extension provides floating-point memory operations.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
@item XTheadFmv
The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register.
It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}.
@item XTheadMac
The XTheadMac extension provides multiply-accumulate instructions.

11
gas/testsuite/gas/riscv/x-thead-fmv.d Normal file
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@ -0,0 +1,11 @@
#as: -march=rv32i_xtheadfmv
#source: x-thead-fmv.s
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0

3
gas/testsuite/gas/riscv/x-thead-fmv.s Normal file
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@ -0,0 +1,3 @@
target:
th.fmv.hw.x a0, fa1
th.fmv.x.hw a1, fa0

8
include/opcode/riscv-opc.h
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@ -2208,6 +2208,11 @@
#define MASK_TH_FSURD 0xf800707f
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
#define MATCH_TH_FMV_HW_X 0x6000100b
#define MASK_TH_FMV_HW_X 0xfff0707f
#define MATCH_TH_FMV_X_HW 0x5000100b
#define MASK_TH_FMV_X_HW 0xfff0707f
/* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f
@ -3122,6 +3127,9 @@ DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD)
DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW)
DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD)
DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
/* Vendor-specific (T-Head) XTheadFmv instructions. */
DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X)
DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW)
/* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)

1
include/opcode/riscv.h
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@ -416,6 +416,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADFMEMIDX,
INSN_CLASS_XTHEADFMV,
INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADMEMIDX,
INSN_CLASS_XTHEADMEMPAIR,

4
opcodes/riscv-opc.c
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@ -1931,6 +1931,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadFmv instructions. */
{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0},
{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0},