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RISC-V: Add T-Head Fmv vendor extension

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This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
2022-11-13 16:59:20 +01:00
committed by Nelson Chu
parent 7a4ce4a1bc
commit 4a3bc79bf4
8 changed files with 40 additions and 3 deletions
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1
include/opcode/riscv.h
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@ -416,6 +416,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADFMEMIDX,
INSN_CLASS_XTHEADFMV,
INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADMEMIDX,
INSN_CLASS_XTHEADMEMPAIR,