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RISC-V: Add T-Head Fmv vendor extension

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This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.

The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
  https://github.com/riscv-non-isa/riscv-toolchain-conventions

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
2022-11-13 16:59:20 +01:00
committed by Nelson Chu
parent 7a4ce4a1bc
commit 4a3bc79bf4
8 changed files with 40 additions and 3 deletions
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8
include/opcode/riscv-opc.h
View File

@ -2208,6 +2208,11 @@
#define MASK_TH_FSURD 0xf800707f
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
#define MATCH_TH_FMV_HW_X 0x6000100b
#define MASK_TH_FMV_HW_X 0xfff0707f
#define MATCH_TH_FMV_X_HW 0x5000100b
#define MASK_TH_FMV_X_HW 0xfff0707f
/* Vendor-specific (T-Head) XTheadMac instructions. */
#define MATCH_TH_MULA 0x2000100b
#define MASK_TH_MULA 0xfe00707f
@ -3122,6 +3127,9 @@ DECLARE_INSN(th_fsrd, MATCH_TH_FSRD, MASK_TH_FSRD)
DECLARE_INSN(th_fsrw, MATCH_TH_FSRW, MASK_TH_FSRW)
DECLARE_INSN(th_fsurd, MATCH_TH_FSURD, MASK_TH_FSURD)
DECLARE_INSN(th_fsurw, MATCH_TH_FSURW, MASK_TH_FSURW)
/* Vendor-specific (T-Head) XTheadFmv instructions. */
DECLARE_INSN(th_fmv_hw_x, MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X)
DECLARE_INSN(th_fmv_x_hw, MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW)
/* Vendor-specific (T-Head) XTheadMac instructions. */
DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA)
DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH)

1
include/opcode/riscv.h
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@ -416,6 +416,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADCMO,
INSN_CLASS_XTHEADCONDMOV,
INSN_CLASS_XTHEADFMEMIDX,
INSN_CLASS_XTHEADFMV,
INSN_CLASS_XTHEADMAC,
INSN_CLASS_XTHEADMEMIDX,
INSN_CLASS_XTHEADMEMPAIR,