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x86: VP2INTERSECT{D,Q} have mask register destination group

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Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register
source, there's a constraint (need to be even) on the destination
register here.

Adjust "good" test cases accordingly, and add a new test case to check
the warning.
This commit is contained in:
Jan Beulich
2024-11-18 11:45:50 +01:00
parent 3c17b69fa1
commit 497ee27a74
18 changed files with 296 additions and 247 deletions
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2
opcodes/i386-opc.tbl
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@@ -3130,7 +3130,7 @@ enqcmds, 0xf3f8, APX_F(ENQCMD), Modrm|AddrPrefixOpReg|NoSuf|EVexMap4, { Unspecif
// VP2INTERSECT instructions.
vp2intersect<dq>, 0xf268, AVX512_VP2INTERSECT, Modrm|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
vp2intersect<dq>, 0xf268, AVX512_VP2INTERSECT, Modrm|Space0F38|Src1VVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImplicitGroup, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
// VP2INTERSECT instructions end.

4
opcodes/i386-tbl.h
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@@ -42711,7 +42711,7 @@ static const insn_template i386_optab[] =
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_vp2intersectd, 0x68, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
{ 0, 0, 0, 1, 0, 0, 0, 1, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 1, 3, 0, 0, 5, 0, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0, 0 },
{ { 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -42723,7 +42723,7 @@ static const insn_template i386_optab[] =
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_vp2intersectq, 0x68, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
{ 0, 0, 0, 1, 0, 0, 0, 1, 5, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 2, 3, 0, 0, 5, 0, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0, 0 },
{ { 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },