espressif/binutils-gdb
1
0
Fork 0
mirror of https://github.com/espressif/binutils-gdb.git synced 2025-06-20 01:50:24 +08:00
Code Issues Packages Projects Releases Wiki Activity

gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm mode

Browse Source 
This patch fixes a mistake when enabling MVE instructions that disabled support
for single precision vmla and vmul for arm mode.

gas/ChangeLog:
2020-11-12  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 26858
	*  config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT.
	* testsuite/gas/arm/pr26858.s: New test.
	* testsuite/gas/arm/pr26858.d: New test.
This commit is contained in:
Andre Vieira
2020-11-13 08:59:48 +00:00
parent a4ae48ccf8
commit 48f4d8ce96
3 changed files with 16 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
gas/config/tc-arm.c
View File

@ -26518,14 +26518,14 @@ static const struct asm_opcode insns[] =
#define ARM_VARIANT & fpu_vfp_ext_v1
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v6t2
mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1xd
mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
MNCE(vmov, 0, 1, (VMOV), neon_mov),
mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),

8
gas/testsuite/gas/arm/pr26858.d Normal file
View File

@ -0,0 +1,8 @@
# name: PR26858
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
[^>]*> ee266a87 vmul.f32 s12, s13, s14
[^>]*> ee000a81 vmla.f32 s0, s1, s2

6
gas/testsuite/gas/arm/pr26858.s Normal file
View File

@ -0,0 +1,6 @@
.syntax unified
.arch armv8-r
.arm
.fpu fpv5-sp-d16
vmul.f32 s12, s13, s14
vmla.f32 s0, s1, s2